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ADM1166ASUZ-REEL View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADM1166ASUZ-REEL Datasheet PDF : 32 Pages
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ADM1166
Parameter
Min
ANALOG-TO-DIGITAL CONVERTER
Signal Range
0
Input Reference Voltage on
REFIN Pin, VREFIN
Resolution
INL
Gain Error
Conversion Time
Offset Error
Input Noise
AUX1, AUX2 Input Impedance
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x7F Output Voltage
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
INL
DNL
Gain Error
Maximum Load Current (Source)
Maximum Load Current (Sink)
Maximum Load Capacitance
Settling Time to 50 pF Load
Load Regulation
PSRR
1
0.592
0.796
0.996
1.246
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
2.043
Minimum Load Capacitance
1
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge-Pump) Mode
(PDO1 to PDO6)
Output Impedance
VOH
11
VOH
VOH 2
10.5
8
IOUTAVG
Typ Max Unit Test Conditions/Comments
VREFIN V
2.048
V
The ADC can convert signals presented to the VH, VPx,
and VXx pins; VPx and VH input signals are attenuated
depending on the selected range; a signal at the pin
corresponding to the selected range is from 0.573 V to
1.375 V at the ADC input
12
Bits
±2.5 LSB
Endpoint corrected, VREFIN = 2.048 V
±0.05 %
VREFIN = 2.048 V
0.44
ms
One conversion on one channel
84
ms
All 12 channels selected, 16× averaging enabled
±2 LSB
VREFIN = 2.048 V
0.25
LSB rms Direct input (no attenuator)
8
Bits
0.6
0.603 V
0.8
0.803 V
1
1.003 V
1.25 1.253 V
601.25
mV
2.36
mV
±0.75 LSB
±0.4 LSB
1
%
100
μA
100
μA
50 pF
2
μs
2.5
mV
60
dB
40
dB
Six DACs are individually selectable for centering on
one of four output voltage ranges
Same range, independent of center point
Endpoint corrected
Per mA
DC
100 mV step in 20 ns with 50 pF load
2.048
−0.25
0.25
60
2.053 V
mV
mV
μF
dB
No load
Sourcing current, IDACxMAX = −100 μA
Sinking current, IDACxMAX = 100 μA
Capacitor required for decoupling, stability
DC
500
12.5 14 V
12
13.5 V
10
13.5 V
20
μA
IOH = 0 μA
IOH = 1 μA
IOH = 7 μA
2 V < VOH < 7 V
Rev. 0 | Page 5 of 32
 

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