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ADM1030ARQ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADM1030ARQ Intelligent Temperature Monitor and PWM Fan Controller ADI
Analog Devices ADI
ADM1030ARQ Datasheet PDF : 28 Pages
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ADM1030
GENERAL DESCRIPTION
The ADM1030 is a temperature monitor and PWM fan control-
ler for microprocessor-based systems. The device communicates
with the system via a serial System Management Bus. The serial
bus controller has a hardwired address pin for device selection
(Pin 13), a serial data line for reading and writing addresses and
data (Pin 15), and an input line for the serial clock (Pin 16). All
control and programming functions of the ADM1030 are per-
formed over the serial bus. The device also supports the SMBus
Alert Response Address (ARA) function.
INTERNAL REGISTERS OF THE ADM1030
A brief description of the ADM1030’s principal internal regis-
ters is given below. More detailed information on the function of
each register is given in Table XII to Table XXVI.
Configuration Register
Provides control and configuration of various functions on
the device.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADM1030, the first byte
of data is always a register address, which is written to the
Address Pointer Register.
Status Registers
These registers provide status of each limit comparison.
Value and Limit Registers
The results of temperature and fan speed measurements are
stored in these registers, along with their limit values.
Fan Speed Config Register
This register is used to program the PWM duty cycle for the fan.
Offset Registers
Allows the temperature channel readings to be offset by a 5-bit
two’s complement value written to these registers. These values
will automatically be added to the temperature values (or sub-
tracted from if negative). This allows the systems designer to
optimize the system if required, by adding or subtracting up to
15C from a temperature reading.
Fan Characteristics Register
This register is used to select the spin-up time, PWM frequency,
and speed range for the fan used.
THERM Limit Registers
These registers contain the temperature values at which THERM
will be asserted.
TMIN/TRANGE Registers
These registers are read/write registers that hold the minimum
temperature value below which the fan will not run when the
device is in Automatic Fan Speed Control Mode. These regis-
ters also hold the values defining the range over that auto fan
control will be provided, and hence determines the temperature
at which the fan will run at full speed.
SERIAL BUS INTERFACE
Control of the ADM1030 is carried out via the SMBus. The
ADM1030 is connected to this bus as a slave device, under the
control of a master device, e.g., the 810 chipset.
The ADM1030 has a 7-bit serial bus address. When the device
is powered up, it will do so with a default serial bus address.
The five MSBs of the address are set to 01011, the two LSBs
are determined by the logical state of Pin 13 (ADD). This is a
three-state input that can be grounded, connected to VCC, or
left open-circuit to give three different addresses. The state of
the ADD pin is only sampled at power-up, so changing ADD
with power on will have no effect until the device is powered off,
then on again.
Table I. ADD Pin Truth Table
ADD Pin
A1
A0
GND
0
0
No Connect
1
0
VCC
0
1
If ADD is left open-circuit, the default address will be 0101110.
The facility to make hardwired changes at the ADD pin allows
the user to avoid conflicts with other devices sharing the same
serial bus, for example, if more than one ADM1030 is used in
a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition, and shift in the next 8 bits, consisting of a
7-bit address (MSB first) plus an R/W bit that determines the
direction of the data transfer, i.e., whether data will be
written to or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, the master will write to the slave
device. If the R/W bit is a 1, the master will read from the
slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop condi-
tions are established. In WRITE mode, the master will pull
the data line high during the tenth clock pulse to assert a
STOP condition. In READ mode, the master device will
override the acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse. This is
known as No Acknowledge. The master will then take the
data line low during the low period before the tenth clock
pulse, then high during the tenth clock pulse to assert a
STOP condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
REV. A
–7–
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