ADM1026JSTZ View Datasheet(PDF) - Analog Devices

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ADM1026JSTZ

Complete Thermal System Management Controller

Analog Devices 

ADM1026

Table 83. Register 46h, +12 V High Limit (Power-On Default FFh)

Bit Name

R/W Description

7–0 +12 V High Limit

R/W This register contains the high limit of the +12 V analog input channel.

Table 84. Register 47h, −12 V High Limit (Power-On Default FFh)

Bit Name

R/W Description

7–0 −12V High Limit

R/W This register contains the high limit of the −12 V analog input channel.

Table 85. Register 48h, Ext1 Low Limit (Power-On Default 80h)

Bit Name

R/W Description

7–0 Ext1 Low Limit

R/W This register contains the low limit of the Ext1 Temp channel.

Table 86. Register 49h, Ext2 / AIN9 Low Limit (Power-On-Default 80h)

Bit

Name

R/W Description

7–0 Ext2 Temp /AIN9 Low

Limit

R/W This register contains the low limit of the Ext2 Temp/AIN9 channel depending on which bit is

configured.

Table 87. Register 4Ah, 3.3 V STBY Low Limit (Power-On Default 00h)

Bit Name

R/W Description

7–0 3.3 V STBY Low Limit

R/W This register contains the low limit of the 3.3 V STBY analog input channel.

Table 88. Register 4Bh, 3.3 V MAIN Low Limit (Power-On Default 00h)

Bit Name

R/W Description

7–0 3.3 V MAIN Low Limit

R/W This register contains the low limit of the 3.3 V MAIN analog input channel.

Table 89. Register 4Ch, +5V Low Limit (Power-On Default 00h)

Bit Name

R/W Description

7–0 0+5 V Low Limit

R/W This register contains the low limit of the +5 V analog input channel.

Table 90. Register 4Dh, VCCP Low Limit (Power-On Default 00h)

Bit Name

R/W Description

7–0 VCCP Low Limit

R/W This register contains the low limit of the VCCP analog input channel.

Table 91. Register 4Eh, +12V Low Limit (Power-On Default 00h)

Bit Name

R/W Description

7–0 +12 V Low Limit

R/W This register contains the low limit of the +12 V analog input channel.

Table 92. Register 4Fh, –12V Low Limit (Power-On Default 00h)

Bit Name

R/W Description

7–0 −12 V Low Limit

R/W This register contains the low limit of the −12 V analog input channel.

Table 93. Register 50h, AIN0 High Limit (Power-On Default FFh)

Bit Name

R/W Description

7–0 AIN0 High Limit

R/W This register contains the high limit of the AIN0 analog input channel.

Table 94. Register 51h, AIN1 High Limit (Power-On Default FFh)

Bit Name

R/W Description

7–0 AIN1 High Limit

R/W This register contains the high limit of the AIN1 analog input channel.

Table 95. Register 52h, AIN2 High Limit (Power-On Default FFh)

Bit Name

R/W Description

7–0 AIN2 High Limit

R/W This register contains the high limit of the AIN2 analog input channel.

Table 96. Register 53h, AIN3 High Limit (Power-On Default FFh)

Bit Name

R/W Description

7–0 AIN3 High Limit

R/W This register contains the high limit of the AIN3 analog input channel.

Rev. A | Page 50 of 56

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