datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADM1025A View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADM1025A
ADI
Analog Devices ADI
ADM1025A Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADM1025/ADM1025A
If ADD is left open-circuit, the default address will be 0101110.
ADD is sampled only after power-up, so any changes made will
have no effect, unless power is cycled.
The facility to make hardwired changes to A1 and A0 allows the
user to avoid conflicts with other devices sharing the same serial
bus if, for example, more than one ADM1025/ADM1025A is
used in a system. However, as previously mentioned, the ADD
pin may also function as a reset output or interrupt output. Use
of these functions may restrict the addresses that can be set. See
the sections on RST and INT for further information.
The serial bus protocol operates as follows.
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition and shift in the next eight bits, consisting of
a 7-bit address (MSB first) plus an R/W bit, which determines
the direction of the data transfer, i.e., whether data will be
written to or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowledge
Bit. All other devices on the bus now remain idle while the
selected device waits for data to be read from or written to it.
If the R/W bit is a 0, the master will write to the slave device.
If the R/W bit is a 1, the master will read from the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.
3. When all data bytes have been read or written, STOP condi-
tions are established. In WRITE mode, the master will pull
the data line high during the 10th clock pulse to assert a
STOP condition. In READ mode, the master device will
override the Acknowledge Bit by pulling the data line high
during the low period before the 9th clock pulse. This is
known as No Acknowledge. The master will then take the
data line low during the low period before the 10th clock
pulse, then high during the 10th clock pulse to assert a
STOP condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADM1025/ADM1025A, write operations
contain either one or two bytes, and read operations contain one
byte and perform the following functions.
To write data to one of the device data registers or read data
from it, the Address Pointer Register must be set so that the
correct data register is addressed; data can then be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the Address Pointer
Register. If data is to be written to the device, the write operation
contains a second data byte that is written to the register selected
by the Address Pointer Register.
This is illustrated in Figure 2a. The device address is sent over
the bus followed by R/W set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the Address Pointer
Register. The second data byte is the data to be written to the
internal data register.
1
9
1
9
SCL
SDA
0
START BY
MASTER
1
0
1
1 A1 A0 R/W
D7
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADM1025
D6 D5 D4 D3 D2 D1 D0
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
ADM1025
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
ACK. BY STOP BY
ADM1025 MASTER
Figure 2a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
REV. C
–7–
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]