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ADG432TQ View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADG432TQ
ADI
Analog Devices ADI
ADG432TQ Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
ADG431/ADG432/ADG433
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
VL to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Analog, Digital Inputs2 . . . . . . . . . . VSS – 2 V to VDD + 2 V or
30 mA, Whichever Occurs First
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
PIN CONFIGURATION
(DIP/SOIC)
IN1 1
16 IN2
D1 2
15 D2
S1 3
ADG431
ADG432
14 S2
VSS 4 ADG433 13 VDD
GND
5
TOP VIEW
(Not to Scale) 12
VL
S4 6
11 S3
D4 7
10 D3
IN4 8
9 IN3
ORDERING GUIDE
Model1
Temperature Range
Package Options2
ADG431BN
ADG431BR
ADG431TQ
ADG431ABR
ADG432BN
ADG432BR
ADG432TQ
ADG432ABR
ADG433BN
ADG433BR
ADG433ABR
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
Q-16
R-16A3
N-16
R-16A
Q-16
R-16A3
N-16
R-16A
R-16A3
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers.
2N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.
3Trench isolated, latch-up proof parts. See Trench Isolation section.
TERMINOLOGY
VDD
Most positive power supply potential.
VSS
Most negative power supply potential in dual
supplies. In single supply applications, it may be
connected to GND.
VL
GND
Logic power supply (+5 V).
Ground (0 V) reference.
S
Source terminal. May be an input or output.
D
Drain terminal. May be an input or output.
IN
Logic control input.
RON
Ohmic resistance between D and S.
RON vs. VD (VS) The variation in RON due to a change in the ana-
log input voltage with a constant load current.
RON Drift
RON Match
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
Change in RON vs. temperature.
Difference between the RON of any two switches.
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Analog voltage on terminals D, S.
CS (OFF)
CD (OFF)
CD, CS (ON)
CIN
tON
tOFF
tD
Crosstalk
Off Isolation
Charge
Injection
“OFF” switch source capacitance.
“OFF” switch drain capacitance.
“ON” switch capacitance.
Input Capacitance to ground of a digital input.
Delay between applying the digital control input
and the output switching on.
Delay between applying the digital control input
and the output switching off.
“OFF” time or “ON” time measured between the
90% points of both switches, when switching
from one address state to another.
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
A measure of unwanted signal coupling through an
“OFF” switch.
A measure of the glitch impulse transferred from the
digital input to the analog output during switching.
–4–
REV. B
 

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