datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADG1438 View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADG1438 Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADG1438/ADG1439
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 3).
VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.1
Table 7.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11 3
t12
Limit at TMIN, TMAX
20
9
9
5
5
5
5
15
5
5
40
15
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK active edge setup time
Data setup time
Data hold time
SCLK active edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK active edge ignored
SCLK active edge to SYNC falling edge ignored
SCLK rising edge to SDO valid
Minimum RESET pulse width
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V.
3 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.
TIMING DIAGRAM
t10
t1
t9
SCLK
t8
t4
t3
t2
t7
SYNC
DIN
DB7
t6
t5
DB0
RESET
SCLK
SYNC
DIN
t8 t4
t3
t5
t6
DB7
t12
Figure 3. Serial Write Operation
t1
8
t2
DB0 DB7
16
t9
t7
DB0
SDO
INPUT WORD FOR DEVICE N
UNDEFINED
INPUT WORD FOR DEVICE N + 1
t11
DB7
DB0
INPUT WORD FOR DEVICE N
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 9 of 20
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]