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ADF4360-5 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADF4360-5 Integrated Synthesizer and VCO ADI
Analog Devices ADI
ADF4360-5 Datasheet PDF : 24 Pages
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4360-5
CPGND 1
AVDD 2
AGND 3
RFOUTA 4
RFOUTB 5
VVCO 6
PIN 1
IDENTIFIER
ADF4360-5
TOP VIEW
(Not to Scale)
18 DATA
17 CLK
16 REFIN
15 DGND
14 CN
13 RSET
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Function
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2
AVDD
3, 8–11, 22 AGND
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must have the same value as DVDD.
Analog Ground. This is the ground return path of the prescaler and VCO.
4
RFOUTA
VCO Output. The output level is programmable from −4.5 dBm to −13.5 dBm. See the Output Matching section
for a description of the various output stages.
5
RFOUTB
VCO Complementary Output. The output level is programmable from −4.5 dBm to −13.5 dBm. See the Output
Matching section for a description of the various output stages.
6
VVCO
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. VVCO must have the same value as AVDD.
7
VTUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage.
12
CC
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the syn-
thesizer. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
I CPmax
=
11.75
RSET
where RSET = 4.7 kΩ, ICPmax = 2.5 mA.
14
CN
Internal Compensation Node. This pin must be decoupled to VVCO with a 10 µF capacitor.
15
DGND
Digital Ground.
16
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
17
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20
MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
21
DVDD
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD must have the same value as AVDD.
23
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
Taking the pin high powers up the device depending on the status of the power-down bits.
24
CP
Charge Pump Output. When enabled, this provides ± ICP to the external loop filter, which in turn drives the internal VCO.
Rev. A | Page 7 of 24
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