|ADF4360-5||Integrated Synthesizer and VCO|
|ADF4360-5 Datasheet PDF : 24 Pages |
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package lead length and 0.05 mm wider than
the package lead width. The lead should be centered on the pad
to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that short-
ing is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 ounce
of copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
There are a number of ways to match the output of the
ADF4360-5 for optimum operation; the most basic is to use a
50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is con-
nected in series as shown Figure 21. Because the resistor is not
frequency dependent, this provides a good broadband match.
The output power in this circuit typically gives −4.5 dBm output
power into a 50 Ω load.
Figure 21. Simple ADF4360-5 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match and, therefore, more
output power. Additionally, a series inductor is added after the
dc bypass capacitor to provide a resonant LC circuit. This tunes
the oscillator output and provides approximately 10 dB addi-
tional rejection of the second harmonic. The shunt inductor
needs to be a relatively high value (>40 nH).
Experiments have shown that the circuit shown in Figure 22
provides an excellent match to 50 Ω over the operating range of
the ADF4360-5. This gives approximately −3 dBm output power
across the frequency range of the ADF4360-5. Both single-
ended architectures can be examined using the EVAL-
ADF4360-5EB1 evaluation board.
Figure 22. Optimum ADF4360-5 Output Stage
If the user does not need the differential outputs available on
the ADF4360-5, the user may either terminate the unused out-
put or combine both outputs using a balun. The circuit in
Figure 23 shows how best to combine the outputs.
Figure 23. Balun for Combining ADF4360-5 RF Outputs
The circuit in Figure 23 is a lumped-lattice-type LC balun. It is
designed for a center frequency of 1.3 GHz and outputs 5.0 dBm
at this frequency. The series 5.1 nH inductor is used to tune out
any parasitic capacitance due to the board layout from each
input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by −90°, thus
combining the two. The action of the 6.8 nH inductor and the
2.2 pF capacitor accomplishes this. The 47 nH is used to provide
an RF choke to feed the supply voltage, and the 10 pF capacitor
provides the necessary dc block. To ensure good RF perform-
ance, the circuits in Figure 22 and Figure 23 are implemented
with Coilcraft 0402/0603 inductors and AVX 0402 thin-film
Alternatively, instead of the LC balun shown in Figure 23, both
outputs may be combined using a 180° rat-race coupler.
Rev. A | Page 22 of 24
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