
Part Name  Description  Manufacturer 
ADF43600BCPZRL  Integrated Synthesizer and VCO  Analog Devices 
ADF43600BCPZRL Datasheet PDF : 24 Pages

Data Sheet
ADF43600
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
powerdown is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on powerdown.
POWERDOWN
CONTROL
NC 100kΩ
REFIN NC
SW2
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 10. Reference Input Stage
PRESCALER (P/P + 1)
The dualmodulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dualmodulus prescaler, operating at CML
levels, takes the clock from the VCO and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17, or 32/33 and is based on a synchronous 4/5 core. There is
a minimum divide ratio possible for fully contiguous output
frequencies; this minimum is determined by P, the prescaler
value, and is given by (P2 − P).
A AND B COUNTERS
The A and B CMOS counters combine with the dualmodulus
prescaler to allow a wide range division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with a VCO
frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dualmodulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
VCO frequency equation is
fVCO = [(P × B)+ A]× fREFIN / R
where:
fVCO is the output frequency of the VCO.
P is the preset modulus of the dualmodulus prescaler (8/9,
16/17, and so on).
B is the preset divide ratio of the binary 13bit counter (3 to 8191).
A is the preset divide ratio of the binary 5bit swallow counter (0 to 31).
fREFIN is the external reference frequency oscillator.
FROM VCO
N = BP + A
PRESCALER
P/P+1
MODULUS
CONTROL
13BIT B
COUNTER
LOAD
LOAD
5BIT A
COUNTER
TO PFD
N DIVIDER
Figure 11. A and B Counters
R COUNTER
The 14bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 12 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in the R counter latch, ABP2 and ABP1, control the width
of the pulse (see Table 9).
UP
HI
D1
Q1
U1
VP CHARGE
PUMP
R DIVIDER
CLR1
PROGRAMMABLE
U3
DELAY
ABP1
ABP2
HI
N DIVIDER
CLR2
DOWN
D2
Q2
U2
CP
CPGND
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 12. PFD Simplified Schematic and Timing (In Lock)
Rev. B  Page 9 of 24

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