ADF4360-0BCPZ View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADF4360-0BCPZ

Integrated Synthesizer and VCO

Analog Devices 

ADF4360-0

POWER-UP

Power-Up Sequence

The correct programming sequence for the ADF4360-0 after

power-up is:

1. R counter latch

2. Control latch

3. N counter latch

Initial Power-Up

Initial power-up refers to programming the part after the

application of voltage to the AVDD, DVDD, VVCO, and CE pins. On

initial power-up, an interval is required between programming

the control latch and programming the N counter latch.

Data Sheet

This interval is necessary to allow the transient behavior of the

ADF4360-0 during initial power-up to have settled. During

initial power-up, a write to the control latch powers up the part

and the bias currents of the VCO begin to settle. If these

currents have not settled to within 10% of their steady-state

value and if the N counter latch is then programmed, the VCO

may not be able to oscillate at the desired frequency, which does

not allow the band select logic to choose the correct frequency

band and the ADF4360-0 may not achieve lock. If the

recommended interval is inserted and the N counter latch is

programmed, the band select logic can choose the correct

frequency band and the part locks to the correct frequency.

This duration of this interval is affected by the value of the

capacitor on the CN pin (Pin 14). This capacitor is used to

reduce the close-in noise of the ADF4360-0 VCO. The

recommended value of this capacitor is 10 μF. Using this value

requires an interval of ≥ 5 ms between the latching in of the

control latch bits and latching in of the N counter latch bits. If a

shorter delay is required, this capacitor can be reduced. A slight

phase noise penalty is incurred by this change, which is

explained further in Table 10.

Table 10. CN Capacitance vs. Interval and Phase Noise

CN value Recommended Interval between Control Latch and N Counter Latch

10 μF

≥ 5 ms

440 nF

≥ 600 μs

Open Loop Phase Noise @ 10 kHz Offset

−84 dBc

−82 dBc

POWER-UP

CLOCK

DATA

LE

R COUNTER

LATCH DATA

CONTROL

LATCH DATA

N COUNTER

LATCH DATA

REQUIRED INTERVAL

CONTROL LATCH WRITE TO

N COUNTER LATCH WRITE

Figure 16. ADF4360-0 Power-Up Timing

Rev. B | Page 16 of 24

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