datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADF4156BCPZ-RL7 View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADF4156BCPZ-RL7
ADI
Analog Devices ADI
ADF4156BCPZ-RL7 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element that sets the width of the antibacklash pulse, which is
typically 3 ns. This pulse ensures that there is no dead zone in the
PFD transfer function, and gives a consistent reference spur level.
HI
+IN
UP
D1 Q1
U1
CLR1
DELAY
U3
CHARGE
PUMP
CP
HI
–IN
CLR2 DOWN
D2 Q2
U2
Figure 14. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4156 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M4, M3, M2, and M1 (for details,
see Figure 16). Figure 15 shows the MUXOUT section in block
diagram form.
THREE-STATE OUTPUT
DVDD
DGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
R DIVIDER/2
N DIVIDER/2
MUX
CONTROL
Figure 15. MUXOUT Schematic
DVDD
MUXOUT
DGND
ADF4156
INPUT SHIFT REGISTERS
The ADF4156 digital section includes a 5-bit RF R counter,
a 12-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of five latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2 and C1) in the shift
register. These are the 3 LSBs, DB2, DB1, and DB0, as shown in
Figure 2. The truth table for these bits is shown in Table 6.
Figure 16 shows a summary of how the latches are programmed.
PROGRAM MODES
Table 6 and Figure 16 through Figure 20 show how to set up the
program modes in the ADF4156.
A number of settings in the ADF4156 are double buffered.
These include the modulus value, phase value, R counter value,
reference doubler, reference divide-by-2, and current setting.
This means that two events have to occur before the part uses a
new value of any of the double buffered settings. First, the new
value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R0.
For example, any time that the modulus value has been
updated, Register R0 must be written to after this, to ensure that
the modulus value is loaded correctly.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3
C2
C1
Register
0
0
0
Register R0
0
0
1
Register R1
0
1
0
Register R2
0
1
1
Register R3
1
0
0
Register R4
Rev. 0 | Page 9 of 24
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]