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Part Name  ADF4156BCPZRL  Analog Devices 
Description  6 GHz FractionalN Frequency Synthesizer 
ADF4156BCPZRL Datasheet PDF : 24 Pages

ADF4156
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
powerdown is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on powerdown.
POWERDOWN
CONTROL
NC 100kΩ
REFIN NC
SW2
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
2stage limiting amplifier to generate the currentmode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
2kΩ
2kΩ
AVDD
RFINA
RFINB
Figure 12. RF Input Stage
AGND
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RFOUT) equation is
RFOUT = FPFD × (INT + (FRAC/MOD))
(1)
where RFOUT is the output frequency of external voltage
controlled oscillator (VCO).
FPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
T is the REFIN divideby2 bit (0 or 1).
R is the preset divide ratio of binary 5bit programmable
reference counter (1 to 32).
INT is the preset divide ratio of binary 12bit counter
(23 to 4095).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD−1).
RF N DIVIDER
FROM RF
INPUT STAGE
N COUNTER
N = INT + FRAC/MOD
TO PFD
THIRD ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
MOD
REG
FRAC
VALUE
Figure 13. RF INT Divider
RF R COUNTER
The 5bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 32 are allowed.
Rev. 0  Page 8 of 24

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