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ADF4156BCPZ-RL View Datasheet(PDF) - Analog Devices

Part NameADF4156BCPZ-RL ADI
Analog Devices ADI
Description6 GHz Fractional-N Frequency Synthesizer
ADF4156BCPZ-RL Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF4156
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless
otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency3
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD
NOISE CHARACTERISTICS
Normalized Phase Noise Floor4
Phase Noise Performance5
5800 MHz Output6
B Version
0.5/6.0
10/250
0.4/AVDD
10
±100
32
5
312.5
2.5
2.7/10
1
2
2
2
1.4
0.6
±1
10
1.4
VDD – 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
32
−211
−89
Unit
GHz min/max
MHz min/max
V p-p min/max
pF max
μA max
MHz max
mA typ
μA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
μA max
pF max
V min
V min
μA max
V max
V min/V max
V min/V max
mA max
dBc/Hz typ
dBc/Hz typ
Test Conditions/Comments1
−10 dBm min to 0 dBm max; for lower frequencies,
ensure slew rate (SR) > 400 V/μs
For f < 10 MHz, use a dc-coupled CMOS-compatible
square wave, slew rate > 25 V/μs
Biased at AVDD/22
Programmable
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
Sink and source current
0.5 V < VCP < VP – 0.5
0.5 V < VCP < VP – 0.5
VCP = VP/2
Open-drain output chosen; 1 kΩ pull-up to 1.8 V
CMOS output chosen
IOL = 500 μA
26 mA typical
@ VCO output
@ 5 kHz offset, 25 MHz PFD frequency
1 Operating temperature for B version: −40°C to +85°C.
2 AC coupling ensures AVDD/2 bias.
3 Guaranteed by design. Sample tested to ensure compliance.
4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(fPFD) + 20logN to calculate in-band phase noise performance as seen
at the VCO output. The value given is the lowest noise mode.
5 The phase noise is measured with the EVAL-ADF4156EB1 evaluation board and the Agilent E5500 phase noise system.
6 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 5800 MHz; N = 232; loop B/W = 20 kHz, ICP = 313 μA; lowest noise mode.
Rev. 0 | Page 3 of 24
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GENERAL DESCRIPTION
The ADF4156 is a 6 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (Σ-Δ) based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry leading to faster lock times without the
need for modifications to the loop filter.

FEATURES
RF bandwidth to 6 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with
ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/
ADF4153 and ADF4154 frequency synthesizers
Programmable RF output phase
Loop filter design possible with ADISimPLL
Cycle slip reduction for faster lock times

APPLICATIONS
CATV equipment
Base stations for mobile radio (WiMAX, GSM, PCS, DCS,
SuperCell 3G, CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs, PMR
Communications test equipment

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