|ADF4156BRUZ-RL||6 GHz Fractional-N Frequency Synthesizer|
|ADF4156BRUZ-RL Datasheet PDF : 24 Pages |
The evaluation software has a sweep function to sweep the
PHASE word so that the user can observe the spur levels on a
If a look-up table is not used, keep the PHASE word at a
constant value to ensure consistent spur levels on any particular
The output of a fractional-N PLL can settle to any one of MOD
phase offsets with respect to the input reference; where MOD is
the fractional modulus. The PHASE resync feature in the
ADF4156 is used to produce a consistent output phase offset
with respect to the input reference. This is necessary in
applications where the output phase and frequency are
important, such as digital beam forming. See the section,
PHASE Programmability, for how to program a specific RF
output phase when using PHASE resync.
PHASE resync is enabled by setting Bit DB20 and Bit DB19 in
Register R4 to [1, 0]. When PHASE resync is enabled, an
internal timer generates sync signals at intervals of TSYNC given
by the following formula:
TSYNC = CLK_DIV_VALUE × MOD × TPFD
TPFD is the PFD reference period.
CLK_DIV_VALUE is the decimal value programmed in
Bit DB[18:7] of Register R4, and can be any integer in the range
of 1 to 4095.
MOD is the modulus value programmed in Bit DB[14:3] of
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The TSYNC time should be programmed
to a value that is as least as long as the worst-case lock time.
Doing so guarantees that the PHASE resync occurs after the last
cycle slip in the PLL settling transient.
In the example shown in Figure 22, the PFD reference is
25 MHz and MOD = 125 for a 200 kHz channel spacing. TSYNC
is set to 400 μs by programming CLK_DIV_VALUE = 80.
LAST CYCLE SLIP
PLL SETTLES TO
PLL SETTLES TO
–100 0 100 200 300 400 500 600 700 800 900 1000
Figure 22. PHASE Resync Example
In order to program a specific RF output phase, the PHASE
word in Register R1 should be changed. As this word is swept
from 0 to MOD, the RF output phase sweeps over a 360o/MOD
range in steps of 360o/MOD.
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum,
however, RF frequencies lower than this can be used providing
the minimum slew rate specification of 400 V/μs is met. An
appropriate LVDS driver can be used to square up the RF signal
before it is fed back to the ADF4156 RF input. The FIN1001
from Fairchild Semiconductor is one such LVDS driver.
A filter design and analysis program is available to help the user
to implement PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLL software. The software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter
architectures are allowed. In designing the loop filter, the ratio
of PFD frequency to loop bandwidth should be kept >200:1.
This is to attenuate the SDM noise.
Rev. 0 | Page 19 of 24
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