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Part Name  ADF4156BCPZRL  Analog Devices 
Description  6 GHz FractionalN Frequency Synthesizer 
ADF4156BCPZRL Datasheet PDF : 24 Pages

ADF4156
Cycle Slips
Cycle slips occur in integerN/fractionalN synthesizers when
the loop bandwidth is narrow compared to the PFD frequency.
The phase error at the PFD inputs accumulates too fast for the
PLL to correct, and the charge pump temporarily pumps in the
wrong direction. This slows down the lock time dramatically.
The ADF4156 contains a cycle slip reduction circuit to extend
the linear range of the PFD allowing faster lock times without
loop filter changes.
When the ADF4156 detects that a cycle slip is about to occur, it
turns on an extra charge pump current cell. This outputs a
constant current to the loop filter, or removes a constant current
from the loop filter (depending on whether the VCO tuning
voltage needs to increase or decrease to acquire the new
frequency). The effect is that the linear range of the PFD is
increased. Stability is maintained because the current is
constant and is not a pulsed current.
If the phase error increases again to a point where another cycle
slip is likely, the ADF4156 turns on another charge pump cell.
This continues until the ADF4156 detects that the VCO
frequency has gone past the desired frequency. It then begins to
turn off the extra charge pump cells one by one until they have
all been turned off and the frequency is settled.
Up to seven extra charge pump cells can be turned on. In most
applications, it is enough to eliminate cycle slips altogether,
giving much faster lock times.
Setting Bit DB28 in the MOD/R register (R2) to 1 enables cycle
slip reduction. Note that a 45% to 55% duty cycle is needed on
the signal at the PFD in order for CSR to operate correctly.
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractionalN synthesizer and how to minimize them
in the ADF4156.
Fractional Spurs
The fractional interpolator in the ADF4156 is a third order ΣΔ
modulator (SDM) with a modulus (MOD) that is programmable
to any integer value from 2 to 4095. In low spur mode (dither
enabled) the minimum allowable value of MOD is 50. The SDM
is clocked at the PFD reference rate (fPFD) that allows PLL output
frequencies to be synthesized at a channel step resolution of
fPFD/MOD.
In low noise mode (dither off), the quantization noise from the
ΣΔ modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital ΣΔ modulator. For the thirdorder modulator
used in the ADF4156, the repeat length depends on the value of
MOD, as listed in Table 7.
Table 7. Fractional Spurs with Dither Off
Condition (Dither Off)
Repeat
Length
If MOD is divisible by 2, but not 3 2 × MOD
If MOD is divisible by 3, but not 2 3 × MOD
If MOD is divisible by 6
6 × MOD
Otherwise
MOD
Spur Interval
Channel step/2
Channel step/3
Channel step/6
Channel step
In low spur mode (dither enabled), the repeat length is
extended to 221 cycles, regardless of the value of MOD, which
makes the quantization error spectrum look like broadband
noise. This can degrade the inband phase noise at the PLL
output by as much as 10 dB. Therefore, for lowest noise, dither
off is a better choice, particularly when the final loop BW is low
enough to attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation are interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (which is the
whole point of a fractionalN synthesizer) spur sidebands
appear on the VCO output spectrum at an offset frequency that
corresponds to the beat note or difference frequency between
an integer multiple of the reference and the VCO frequency.
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the
reference where the difference frequency can be inside the loop
bandwidth, hence the name integer boundary spurs.
Reference Spurs
Reference spurs are generally not a problem in fractionalN
synthesizers as the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such
mechanism is feed through of low levels of onchip reference
switching noise out through the RFIN pin back to the VCO,
resulting in reference spur levels as high as –90 dBc. Care
should be taken in the PCB layout to ensure that the VCO is
well separated from the input reference to avoid a possible feed
through path on the board.
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the
quantization noise of the SDM also depends on the particular
PHASE word with which the modulator is seeded. Setting the
SD reset bit to zero (DB14 in Register 3) ensures that the SDM
is seeded with the PHASE word on every write to Register 0.
The PHASE word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Thus, a
lookup table of PHASE values corresponding to each frequency
can be constructed for use when programming the ADF4156.
Rev. 0  Page 18 of 24

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