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ADF4156BCPZ-RL View Datasheet(PDF) - Analog Devices

Part NameADF4156BCPZ-RL ADI
Analog Devices ADI
Description6 GHz Fractional-N Frequency Synthesizer
ADF4156BCPZ-RL Datasheet PDF : 24 Pages
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RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be
programmed:
RFOUT = [INT + (FRAC/MOD)] × [FPFD]
(3)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
FPFD = REFIN × [(1 + D)/(R × (1+T))]
(4)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
T is the reference divide-by-2 Bit(0 or 1).
R is the RF reference division factor. For example, in a GSM
1800 system, where 1.8 GHz RF frequency output (RFOUT) is
required, a 13 MHz reference frequency input (REFIN) is
available, and a 200 kHz channel resolution (fRES) is required, on
the RF output.
MOD = REFIN/fRES
MOD = 13 MHz/200 kHz = 65
From Equation 4
FPFD = [13 MHz × (1 + 0)/1] = 13 MHz
(5)
1.8 GHz = 13 MHz × (INT + FRAC/65)
(6)
where INT = 138; FRAC = 30.
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (fRES) required at
the RF output. For example, a GSM system with 13 MHz REFIN sets
the modulus to 65. This means that the RF output resolution (fRES)
is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,
the fractional spur interval depends on the modulus values chosen.
See Table 7 for more information.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important to
note that the PFD cannot be operated above 32 MHz due to a
limitation in the speed of the Σ-Δ circuit of the N-divider.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the cycle slip reduction (CSR)
ADF4156
function. See the Cycle Slip Reduction for Faster Lock Times
section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4156 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configurations
for the application, when combined with the reference doubler
and the 5-bit R counter.
The following is an example of an application that requires
1.75 GHz RF and 200 kHz channel step resolution. The system
has a 13 MHz reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD programming the modulus to divide by 130. This
also results in 200 kHz resolution and offers superior phase
noise performance over the previous setup.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC
and GSM 1800 standards, the programmable modulus is a
great benefit. PDC requires 25 kHz channel step resolution,
whereas GSM 1800 requires 200 kHz channel step resolution.
A 13 MHz reference signal can be fed directly to the PFD and
the modulus can be programmed to 520 when in PDC mode
(13 MHz/520 = 25 kHz).
The modulus needs to be reprogrammed to 65 for GSM 1800
operation (13 MHz/65 = 200 kHz).
It is important that the PFD frequency remains constant (13 MHz).
This allows the user to design one loop filter that can be used in
both setups without running into stability issues. It is the ratio
of the RF frequency to the PFD frequency that affects the loop
design. By keeping this relationship constant, the same loop
filter can be used in both applications.
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
As mentioned in the Noise and Spur Mode section, the
ADF4156 can be optimized for noise performance. However, in
fast-locking applications, the loop bandwidth needs to be wide,
and therefore, the filter does not provide much attenuation of
the spurs. The cycle slip reduction function on the ADF4156
can be used to get around this issue. Using cycle slip reduction,
the loop bandwidth can be kept narrow to attenuate spurs and
still obtain fast lock times.
Rev. 0 | Page 17 of 24
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GENERAL DESCRIPTION
The ADF4156 is a 6 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (Σ-Δ) based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry leading to faster lock times without the
need for modifications to the loop filter.

FEATURES
RF bandwidth to 6 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with
ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/
ADF4153 and ADF4154 frequency synthesizers
Programmable RF output phase
Loop filter design possible with ADISimPLL
Cycle slip reduction for faster lock times

APPLICATIONS
CATV equipment
Base stations for mobile radio (WiMAX, GSM, PCS, DCS,
SuperCell 3G, CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs, PMR
Communications test equipment

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