datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

ADF4156BRUZ-RL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADF4156BRUZ-RL 6 GHz Fractional-N Frequency Synthesizer ADI
Analog Devices ADI
ADF4156BRUZ-RL Datasheet PDF : 24 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
ADF4156
CLK DIV REGISTER, R4
With R3[2,1, 0] set to [1, 0, 0], the on-chip clock divider register
(R4) is programmed. Figure 21 shows the input data format for
programming this register.
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for
activation of PHASE Resync. See the PHASE RESYNC section
for more information.
Clock Divider Mode
These bits must be set to DB[20, 19] = [1, 0] in order to activate
PHASE resync, and 0 otherwise.
RESERVED BITS
All reserved bits should be set to 0 for normal operation.
INITIALIZATION SEQUENCE
After powering up the part, the correct register programming
sequence is:
1. CLK/DIV register (R4)
2. FUNCTION register (R3)
3. MOD/R register (R2)
4. PHASE register (R1)
5. FRAC/INT register (R0)
RESERVED
CLK
DIV
MODE
12-BIT CLOCK DIVIDER VALUE
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 M2 M1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 R4 R3 R2 R1 C3(1) C2(0) C1(0)
M2 M1 OUTPUT
0
0
CLK DIV OFF
0
1
RESERVED
1
0
RESYNC TIMER ENABLED
1
1
RESERVED
D12 D11 .......... D2 D1
0 0 .......... 0 0
0 0 .......... 0 1
0 0 .......... 1 0
0 0 .......... 1 1
.
.
.......... .
.
.
.
.......... .
.
.
.
.......... .
.
1 1 .......... 0 0
1 1 .......... 0 1
1 1 .......... 1 0
1 1 .......... 1 1
CLOCK DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
Figure 21. CLK DIV Register (R4) Map
Rev. 0 | Page 16 of 24
Direct download click here
 

Share Link : ADI
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]