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ADF4156BRUZ-RL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADF4156BRUZ-RL 6 GHz Fractional-N Frequency Synthesizer ADI
Analog Devices ADI
ADF4156BRUZ-RL Datasheet PDF : 24 Pages
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FUNCTION REGISTER, R3
With R2[2, 1, 0] set to [0, 1, 1], the on-chip function register is
programmed. Figure 20 shows the input data format for
programming this register.
RF Counter Reset
DB3 is the RF counter reset bit for the ADF4156. When this is
1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
RF Charge Pump Three-State
DB4 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
RF Power-Down
DB5 on the ADF4156 provides the programmable power-down
mode. Setting this bit to 1 performs a power-down. Setting this
bit to 0 returns the synthesizer to normal operation. While in
software power-down mode, the part retains all information in
its registers. Only when supplies are removed are the register
contents lost.
When a power-down is activated, the following events occur:
1. The synthesizer counters are forced to their load state
conditions.
2. The charge pump is forced into three-state mode.
ADF4156
3. The digital lock detect circuitry is reset.
4. The RFIN input is debiased.
5. The input register remains active and capable of loading
and latching data.
Phase Detector Polarity
DB6 in the ADF4156 sets the phase detector polarity. When the
VCO characteristics are positive, this should be set to 1. When
they are negative, it should be set to 0.
Lock Detect Precision (LDP)
When DB7 is programmed to 0, 40 consecutive PFD cycles of
10 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 6 ns
must occur before digital lock detect is set.
Sigma-Delta (SD) Reset
For most applications, DB14 should be programmed to 0.
When DB14 is programmed to 0, the sigma-delta is reset and
seeded with the PHASE word on every write to Register 0. This
has the effect of producing consistent spur levels.
If it is not required that the sigma-delta be reset on each write to
Register 0, this bit should be set to 1.
RESERVED
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U12 0 0 0 0 0 0 U11 U10 U9 U8 U7 C3(0) C2(1) C1(1)
U12 SD RESET
0 ENABLED
1 DISABLED
Figure 20. Function Register (R3) Map
U11 LDP
0
10ns
1
6ns
U10 PD POLARITY
0 NEGATIVE
1 POSITIVE
U7
COUNTER
RESET
0 DISABLED
1 ENABLED
U8
CP
THREE-STATE
0 DISABLED
1 ENABLED
U9 POWER DOWN
0 DISABLED
1 ENABLED
Rev. 0 | Page 15 of 24
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