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ADF4156BCPZ-RL View Datasheet(PDF) - Analog Devices

Part NameADF4156BCPZ-RL ADI
Analog Devices ADI
Description6 GHz Fractional-N Frequency Synthesizer
ADF4156BCPZ-RL Datasheet PDF : 24 Pages
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MOD/R REGISTER, R2
With R1[2, 1, 0] set to [0, 1, 0], the on-chip MOD/R register is
programmed. Figure 19 shows the input data format for
programming this register.
Noise and Spur Mode
The noise modes on the ADF4156 are controlled by DB30 and
DB29 in the MOD/R register. See Figure 19 for the truth table.
The noise modes allow the user to optimize a design either for
improved spurious performance or for improved phase noise
performance.
When the lowest spur setting is chosen, dither is enabled. This
randomizes the fractional quantization noise so that it
resembles white noise rather than spurious noise. As a result,
the part is optimized for improved spurious performance. This
operation would normally be used when the PLL closed-loop
bandwidth is wide, for fast-locking applications. (Wide loop
bandwidth is seen as a loop bandwidth greater than 1/10 of the
RFOUT channel step resolution (fRES)). A wide loop filter does not
attenuate the spurs to the same level as a narrow loop bandwidth.
For best noise performance, use the lowest noise setting option.
As well as disabling the dither, it also ensures that the charge
pump is operating in an optimum region for noise performance.
This setting is extremely useful where a narrow loop filter band-
width is available. The synthesizer ensures extremely low noise
and the filter attenuates the spurs. The typical performance
characteristics give the user an idea of the trade-off in a typical
WCDMA setup for the different noise and spur settings.
CSR Enable
Setting this bit to 1 enables cycle slip reduction. This is a
method for improving lock times. Note that the signal at the
phase frequency detector (PFD) must have a 50% duty cycle in
order for cycle slip reduction to work. The charge pump current
setting must also be set to a minimum. See the section, Cycle
Slip Reduction for Faster Lock Times, for more information.
Charge Pump Current Setting
DB27, DB26, DB25, and DB24 set the charge pump current
setting. This should be set to the charge pump current that the
loop filter is designed with (see Figure 19).
Prescaler (P/P + 1)
The dual modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RFIN to the PFD input.
ADF4156
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on a
synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating the
ADF4156 above 3 GHz, this must be set to 8/9. The prescaler
limits the INT value.
With P = 4/5, NMIN = 23.
With P = 8/9, NMIN = 75.
RDIV/2
Setting this bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and PFD, which extends the maximum
REFIN input rate.
Reference Doubler
Setting DB20 to 0 feeds the REFIN signal directly to the 5-bit RF
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before feeding into the 5-bit
R counter. When the doubler is disabled, the REFIN falling edge
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising and falling edges
of REFIN become active edges at the PFD input.
When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to the
REFIN duty cycle. The phase noise degradation can be as much
as 5 dB for the REFIN duty cycles outside a 45% to 55% range.
The phase noise is insensitive to the REFIN duty cycle in the
lowest noise mode. The phase noise is insensitive to REFIN duty
cycle when the doubler is disabled.
The maximum allowable REFIN frequency when the doubler is
enabled is 30 MHz.
5-Bit R Counter
The 5-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the phase frequency detector (PFD). Division ratios from
1 to 32 are allowed.
12-Bit Interpolator MOD Value
This programmable register sets the fractional modulus. This is
the ratio of the PFD frequency to the channel step resolution on
the RF output. Refer to the RF Synthesizer: A Worked Example
section for more information.
Rev. 0 | Page 13 of 24
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GENERAL DESCRIPTION
The ADF4156 is a 6 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (Σ-Δ) based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry leading to faster lock times without the
need for modifications to the loop filter.

FEATURES
RF bandwidth to 6 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with
ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/
ADF4153 and ADF4154 frequency synthesizers
Programmable RF output phase
Loop filter design possible with ADISimPLL
Cycle slip reduction for faster lock times

APPLICATIONS
CATV equipment
Base stations for mobile radio (WiMAX, GSM, PCS, DCS,
SuperCell 3G, CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs, PMR
Communications test equipment

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