ADF4154BRUZ-RL View Datasheet(PDF) - Analog Devices
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ADF4154BRUZ-RL Datasheet PDF : 24 Pages
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Data Sheet
ADF4154
SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm
referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)1
REFERENCE CHARACTERISTICS
REFIN Input Frequency1
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency3
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD, SDVDD
VP
IDD
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH) 4
Normalized 1/f Noise (PN1_f)5
Phase Noise Performance6
1750 MHz Output7
B Version
0.5/4.0
1.0/4.0
10/250
0.7/AVDD
10
±100
Unit
GHz min/max
GHz min/max
MHz min/max
V p-p min/max
pF max
µA max
Test Conditions/Comments
See Figure 15 for the input circuit.
−8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 400 V/µs.
−10 dBm/0 dBm min/max.
See Figure 14 for input circuit.
For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave,
slew rate > 25 V/µs.
Biased at AVDD/2.2
32
MHz max
5
312.5
2.5
2.7/10
1
2
2
2
mA typ
µA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
Programmable. See Table 5.
With RSET = 5.1 kΩ.
With RSET = 5.1 kΩ.
Sink and source current.
0.5 V < VCP < VP − 0.5 V.
0.5 V < VCP < VP − 0.5 V.
VCP = VP/2.
1.4
V min
0.6
V max
±1
µA max
10
pF max
1.4
V min
0.4
V max
Open-drain 1 kΩ pull-up to 1.8 V.
IOL = 500 µA.
2.7/3.3
AVDD
AVDD/5.5
24
1
V min/V max
V min/V max
mA max
µA typ
20 mA typical.
−220
−114
−102
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
PLL loop BW = 500 kHz.
Measured at 100 kHz offset.
10 kHz offset; normalized to 1GHz.
@ VCO output.
@ 1 kHz offset, 26 MHz PFD frequency.
1 Use a square wave for frequencies below fMIN.
2 AC coupling ensures AVDD/2 bias. See Figure 14 for a typical circuit.
3 Guaranteed by design. Sample tested to ensure compliance.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at a frequency offset f is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6 The phase noise is measured with the EVAL-ADF4154EB1 and the HP8562E spectrum analyzer.
7 fREFIN = 26 MHz, fPFD = 26 MHz, offset frequency = 1 kHz, RFOUT = 1750 MHz, loop B/W = 20 kHz, lowest noise mode.
Rev. C | Page 3 of 24
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