ADF4154BRU View Datasheet(PDF) - Analog Devices

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Description

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ADF4154BRU

Fractional-N Frequency Synthesizer

Analog Devices 

Data Sheet

RF Charge Pump Three-State

This bit (DB3) puts the charge pump into three-state mode when it

is programmed to 1. For normal operation, it should be set to 0.

RF Power-Down

DB4 on the ADF4154 provides the programmable power-down

mode. Setting Bit DB4 to 1 powers down the device. Setting

Bit DB4 to 0 returns the synthesizer to normal operation. While

in software power-down mode, the part retains all information

in its registers. Only when supplies are removed are the register

contents lost.

When a power-down is activated, the following events occur:

1. All active dc current paths are removed.

2. The synthesizer counters are forced to their load

state conditions.

3. The charge pump is forced into three-state mode.

4. The digital lock detect circuitry is reset.

5. The RFIN input is debiased.

6. The input register remains active and capable of loading

and latching data.

Lock Detect Precision (LDP)

When the LDP bit (DB5) is programmed to 0, 24 consecutive

reference cycles of 15 ns must occur before the digital lock detect is

set. When this bit is programmed to 1, 40 consecutive reference

cycles of 15 ns must occur before digital lock detect is set.

Phase Detector Polarity

DB6 sets the phase detector polarity. When the VCO characteristics

are positive, this bit should be set to 1. When they are negative,

this bit should be set to 0.

Charge Pump (CP) Current Setting and CP/2

DB7, DB8, DB9, and DB10 set the charge pump current, which

should be set according to the loop filter design (see Table 9).

REFIN Doubler

Setting the REFIN doubler bit (DB11) to 0 feeds the REFIN signal

directly to the 4-bit R-counter, which disables the doubler.

Setting the REFIN doubler bit to 1 multiplies the REFIN frequency

by a factor of 2 before feeding into the 4-bit R-counter. When

the doubler is disabled, the REFIN falling edge is the active edge

at the PFD input to the fractional synthesizer. When the doubler

is enabled, both the rising and falling edges of REFIN become

active edges at the PFD input.

When the doubler is enabled and the lowest spur mode is

chosen, the in-band phase noise performance is sensitive to the

REFIN duty cycle. The phase noise degradation can be as much

as 5 dB for the REFIN duty cycles outside a 45% to 55% range.

The phase noise is insensitive to the REFIN duty cycle in the

lowest noise mode and in the lowest noise and spur mode. The

phase noise is insensitive to the REFIN duty cycle when the

doubler is disabled.

ADF4154

The maximum allowed REFIN frequency when the doubler is

enabled is 30 MHz.

NOISE AND SPUR REGISTER, R3

The on-chip noise and spur register is programmed by setting

R3 [1, 0] to [1, 1].

Table 10 shows the input data format for programming this

register.

Noise and Spur Mode

Noise and spur mode allows the user to optimize a design either

for improved spurious performance or for improved phase noise

performance. When the lowest spur setting is chosen, dither is

enabled. This randomizes the fractional quantization noise so

that it looks more like white noise than spurious noise, meaning

that the part is optimized for improved spurious performance.

This operation is typically used when the PLL closed-loop band-

width is wide for fast-locking applications. A wide-loop bandwidth

is defined as a loop bandwidth greater than 1/10 of the RFOUT

channel step resolution (fRES). A wide-loop filter does not attenuate

the spurs to a level that a narrow-loop bandwidth would. When

the low noise and spur setting is enabled, dither is disabled.

This optimizes the synthesizer to operate with improved noise

performance. However, the spurious performance is degraded

in this mode compared with the lowest spur setting. To further

improve noise performance, the lowest noise setting option can

be used, which reduces the phase noise. As well as disabling the

dither, it ensures that the charge pump operates in an optimum

region for noise performance. This setting is extremely useful if

a narrow-loop filter bandwidth is used. The synthesizer ensures

extremely low noise, and the filter attenuates the spurs. The

typical performance characteristics show the trade-offs in a

typical WCDMA setup for different noise and spur settings.

RESERVED BITS

These bits should be set to 0 for normal operation.

Rev. C | Page 17 of 24

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