ADE3700X View Datasheet(PDF) - STMicroelectronics

Part Name

Description

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ADE3700X

Analog LCD Display Engine for XGA and SXGA Resolutions

STMicroelectronics 

ADE3700

2 Functional Description

Global Control

2.1 Global Control

The global control block is responsible for:

q selecting clock sources

q power control

q I²C control

q SCLK frequency synthesizer control

q block by block synchronous reset generation

The global control block runs on the XCLK clock domain which is required to be active for

programming. The clock domains of all other blocks are set in the Global Control Block. For I²C

access, the requested block must be driven with a valid clock frequency greater than 10 MHz. Clock

domains are shown in Figure 2.

Figure 2: Global Control Block Diagram

MCU (SCL, SDA)

PC Analog

INR, G, B

V, H, Csync

I²C

Global

PWM

Sync

Measure

XCLK

Domain

Sync

Re-Time

ADC (Analog)

Data

ADC Digital I/F

LCD Scaler

ADE3700

Flicker

Detection

Line Lock

PLL

Data

Measure

INCLK

Domain

SCLK

Domain

SCLK Freq.

Synthesizer

Output

Sequencer

TCON

DOTCLK

Domain

FM Freq.

Synthesizer

ORA

OGA

OBA

ORB

OGB

OBB

OCLK

ODE

OHS

OVS

TCON

To program the SCLK frequency synthesizer to a desired frequency (fOUT, in MHz), the following

equations apply.

Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet 1 of 2)

Frequency Range

fOUT < 8 x fXCLK AND fOUT ≥ 4 x fXCLK

fOUT < 4 x fXCLK AND fOUT ≥ 2 x fXCLK

SDIV

0

1

11/89

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