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ADF4112BRUZ-REEL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADF4112BRUZ-REEL RF PLL Frequency Synthesizers ADI
Analog Devices ADI
ADF4112BRUZ-REEL Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF4110/ADF4111/ADF4112/ADF4113
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RSET 1
16 VP
CP 2 ADF4110 15 DVDD
CPGND 3 ADF4111 14 MUXOUT
AGND 4 ADF4112 13 LE
ADF4113
RFINB 5
12 DATA
RFINA 6 TOP VIEW 11 CLK
AVDD 7 (Not to Scale) 10 CE
REFIN 8
9 DGND
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
ADF4110
ADF4111
ADF4112
ADF4113
TOP VIEW
(Not to Scale)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No. Mnemonic
1
19
RSET
2
20
CP
3
1
CPGND
4
2, 3
AGND
5
4
RFINB
6
5
RFINA
7
6, 7
AVDD
8
8
REFIN
9
9, 10
DGND
10
11
CE
11
12
CLK
12
13
DATA
13
14
LE
14
15
MUXOUT
15
16, 17
DVDD
16
18
VP
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
I CPmax
=
23.5
RSET
So, with RSET = 4.7 kΩ, ICPmax = 5 mA.
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 29.
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. AVDD must be the same value
as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2, and an equivalent input
resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator,
or can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device depending on the status of the power-
down Bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital
ground plane should be placed as close as possible to this pin. DVDD must be the same value
as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is
3 V, VP can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.
Rev. C | Page 7 of 28
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