|ADF4110BRU-REEL||RF PLL Frequency Synthesizers|
|ADF4110BRU-REEL Datasheet PDF : 28 Pages |
RESYNCHRONIZING THE PRESCALER OUTPUT
Table 7 (the Reference Counter Latch Map) shows two bits,
DB22 and DB21, which are labeled DLY and SYNC, respectively.
These bits affect the operation of the prescaler.
With SYNC = 1, the prescaler output is resynchronized with the
RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB improvement
is seen in the ADF4113. The lower bandwidth devices can show
an even greater improvement. For example, the ADF4110 phase
noise is typically improved by 3 dB when SYNC is enabled.
With DLY = 1, the prescaler output is resynchronized with a
delayed version of the RF input.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler coincides with the
active edge on RF input; this causes the SYNC feature to break
down. It is important to be aware of this when using the SYNC
feature. Adding a delay to the RF signal, by programming
DLY = 1, extends the operating frequency and temperature
somewhat. Using the SYNC feature also increases the value of
the AIDD for the device. With a 900 MHz output, the ADF4113
AIDD increases by about 1.3 mA when SYNC is enabled and by
an additional 0.3 mA if DLY is enabled.
All the typical performance plots in this data sheet, except for
Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza-
tion or delay enabled.
Rev. C | Page 21 of 28
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