|ADF4112BRUZ-REEL||RF PLL Frequency Synthesizers|
|ADF4112BRUZ-REEL Datasheet PDF : 28 Pages |
RF PLL Frequency Synthesizers
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downcon-
version sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Communications test equipment
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging from
2.7 V to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER 22
A, B COUNTER
SETTING 1 SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
N = BP + A
M3 M2 M1
Figure 1. Functional Block Diagram
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