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ADF4112BRUZ-REEL View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADF4112BRUZ-REEL
ADI
Analog Devices ADI
ADF4112BRUZ-REEL Datasheet PDF : 28 Pages
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Table 7. Reference Counter Latch Map
ADF4110/ADF4111/ADF4112/ADF4113
DLY SYNC
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X DLY SYNC LDP T2
T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8
R7 R6
R5 R4
R3 R2
R1 C2 (0) C1 (0)
X = DON'T
CARE
R14
R13
R12 ••••••••••
0
0
0
••••••••• •
0
0
0
••••••••• •
0
0
0
••••••••• •
0
0
0
••••••••• •
••••••••• •
••••••••• •
••••••••• •
1
1
1
••••••••• •
1
1
1
••••••••• •
1
1
1
••••••••• •
1
1
1
••••••••• •
R3
R2
R1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
1
0
1
1
1
0
1
1
1
DIVIDE RATIO
1
2
3
4
16380
16381
16382
16383
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0
0
3.0ns
0
1
1
0
1
1
1.5ns
6.0ns
3.0ns
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
LDP
0
1
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
DLY SYNC OPERATION
0
0
NORMAL OPERATION
0
1
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
1
0
NORMAL OPERATION
1
1
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
Rev. C | Page 15 of 28
 

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