ADF4108BCPZ View Datasheet(PDF) - Analog Devices

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ADF4108BCPZ

PLL Frequency Synthesizer

Analog Devices 

Charge Pump Currents

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge

pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the

charge pump. The truth table is given in Figure 19.

Prescaler Value

P2 and P1 in the function latch set the prescaler values. The

prescaler value should be chosen so that the prescaler output

frequency is always less than or equal to 300 MHz. Thus, with

an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but

a value of 8/9 is not valid.

PD Polarity

This bit sets the phase detector polarity bit. See Figure 19.

CP Three-State

This bit controls the CP output pin. With the bit set high, the

CP output is put into three-state. With the bit set low, the CP

output is enabled.

INITIALIZATION LATCH

The initialization latch is programmed when C2 and C1 are set

to 1 and 1. This is essentially the same as the function latch

(programmed when C2, C1 = 1, 0).

However, when the initialization latch is programmed, an

additional internal reset pulse is applied to the R and AB

counters. This pulse ensures that the AB counter is at load point

when the AB counter data is latched and the device will begin

counting in close phase alignment.

If the latch is programmed for synchronous power-down (CE

pin is high; PD1 bit is high; PD2 bit is low), the internal pulse

also triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse

and so close phase alignment is maintained when counting

resumes.

When the first AB counter data is latched after initialization, the

internal reset pulse is again activated. However, successive AB

counter loads after this will not trigger the internal reset pulse.

Device Programming after Initial Power-Up

After initially powering up the device, there are three ways to

program the device.

Initialization Latch Method

1. Apply VDD.

2. Program the initialization latch (11 in 2 LSBs of input

word). Make sure that the F1 bit is programmed to 0.

3. Next, do a function latch load (10 in 2 LSBs of the control

word), making sure that the F1 bit is programmed to a 0.

4. Then do an R load (00 in 2 LSBs).

5. Then do an AB load (01 in 2 LSBs).

ADF4108

When the initialization latch is loaded, the following occurs:

• The function latch contents are loaded.

• An internal pulse resets the R, AB, and timeout counters to

load-state conditions and also three-states the charge pump.

Note that the prescaler band gap reference and the oscillator

input buffer are unaffected by the internal reset pulse, allowing

close phase alignment when counting resumes.

• Latching the first AB counter data after the initialization word

will activate the same internal reset pulse. Successive AB loads

will not trigger the internal reset pulse unless there is another

initialization.

CE Pin Method

1. Apply VDD.

2. Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

3. Program the function latch (10).

4. Program the R counter latch (00).

5. Program the AB counter latch (01).

6. Bring CE high to take the device out of power-down. The R

and AB counters will now resume counting in close

alignment.

Note that after CE goes high, a duration of 1 μs may be required

for the prescaler band gap voltage and oscillator input buffer

bias to reach steady state.

CE can be used to power the device up and down to check for

channel activity. The input register does not need to be

reprogrammed each time the device is disabled and enabled as

long as it has been programmed at least once after VDD was

initially applied.

Counter Reset Method

1. Apply VDD.

2. Do a function latch load (10 in 2 LSBs). As part of this,

load 1 to the F1 bit. This enables the counter reset.

3. Do an R counter load (00 in 2 LSBs).

4. Do an AB counter load (01 in 2 LSBs).

5. Do a function latch load (10 in 2 LSBs). As part of this,

load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the

initialization method. It offers direct control over the internal

reset. Note that counter reset holds the counters at load point

and three-states the charge pump, but does not trigger

synchronous power-down.

POWER SUPPLY CONSIDERATIONS

The ADF4108 operates over a power supply range of 3.2 V to

3.6 V. The ADP3300ART-3.3 is a low dropout linear regulator

from Analog Devices. It outputs 3.3 V with an accuracy of 1.4%

and is recommended for use with the ADF4108.

Rev. 0 | Page 17 of 20

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