datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADF4107BRU View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADF4107BRU
ADI
Analog Devices ADI
ADF4107BRU Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Data Sheet
ADF4107
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)3
RF Input Sensitivity
Maximum Allowable Prescaler Output
Frequency4
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity5
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency7
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
B Version1
1.0/7.0
–5/+5
300
20/250
0.8/VDD
10
±100
104
5
625
2.5
3.0 to 11
1
2
1.5
2
1.4
0.6
±1
10
1.4
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD8 (AIDD + DIDD)
IP
Power-Down Mode9 (AIDD + DIDD)
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH)10
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
17
0.4
10
−223
Normalized 1/f Noise (PN1_f)11
−122
B Chips2 (Typ) Unit
Test Conditions/Comments
1.0/7.0
–5/+5
300
GHz min/max
dBm min/max
MHz max
See Figure 18 for input circuit
20/250
0.8/VDD
10
±100
104
5
625
2.5
3.0 to 11
1
2
1.5
2
1.4
0.6
±1
10
1.4
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
15
0.4
10
−223
−122
MHz min/max
V p-p min/max
pF max
µA max
For f < 20 MHz, ensure slew rate >50 V/µs
Biased at AVDD/26
MHz max
ABP = 0,0 (2.9 ns antibacklash pulse width)
Programmable; see Figure 25
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
See Figure 25
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
V min
V max
µA max
pF max
V min
V min
µA max
V max
Open-drain output chosen; 1 kΩ pull-up
resistor to 1.8 V
CMOS output chosen
IOL = 500 µA
V min/V max
V min/V max
mA max
mA max
µA typ
AVDD ≤ VP ≤ 5.5 V
15 mA typ
TA = 25°C
dBc/Hz typ
dBc/Hz typ
PLL loop BW = 500 kHz, measured at
100 kHz offset
10 kHz offset; normalized to 1 GHz
Rev. D | Page 3 of 20
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]