ADF4107BRUZ-REEL7 View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADF4107BRUZ-REEL7

PLL Frequency Synthesizer

Analog Devices 

ADF4107

FUNCTION LATCH

The on-chip function latch is programmed with C2 and C1 set

to 1 and 0, respectively. Figure 25 shows the input data format

for programming the function latch.

Counter Reset

DB2 (F1) is the counter reset bit. When this bit is 1, the R

counter and the AB counters are reset. For normal operation,

this bit should be 0. Upon powering up, the F1 bit needs to be

disabled (set to 0). Then, the N counter resumes counting in

close alignment with the R counter. (The maximum error is one

prescaler cycle).

Power-Down

DB3 (PD1) and DB21 (PD2) provide programmable power-

down modes. They are enabled by the CE pin.

When the CE pin is low, the device is immediately disabled

regardless of the states of PD2 and PD1.

In the programmed asynchronous power-down, the device

powers down immediately after latching a 1 into the PD1 bit,

with the condition that PD2 has been loaded with a 0.

In the programmed synchronous power-down, the device

power-down is gated by the charge pump to prevent unwanted

frequency jumps. Once the power-down is enabled by writing

a 1 into PD1 (on condition that a 1 has also been loaded to

PD2), then the device goes into power-down on the occurrence

of the next charge pump event.

When a power-down is activated (either in synchronous or

asynchronous mode, including CE pin-activated power-down),

the following events occur:

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load state

conditions.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RFIN input is debiased.

• The reference input buffer circuitry is disabled.

• The input register remains active and capable of loading and

latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on

the ADF4107. Figure 25 shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. Fastlock is

enabled only when this bit is 1.

Data Sheet

Fastlock Mode Bit

DB10 of the function latch is the fastlock mode bit. When

fastlock is enabled, this bit determines which fastlock mode is

used. If the fastlock mode bit is 0, then Fastlock Mode 1 is

selected; and if the fastlock mode bit is 1, then Fastlock Mode 2

is selected.

Fastlock Mode 1

The charge pump current is switched to the contents of Current

Setting 2. The device enters fastlock by having a 1 written to the

CP gain bit in the AB counter latch. The device exits fastlock by

having a 0 written to the CP gain bit in the AB counter latch.

Fastlock Mode 2

The charge pump current is switched to the contents of Current

Setting 2. The device enters fastlock by having a 1 written to the

CP gain bit in the AB counter latch. The device exits fastlock

under the control of the timer counter. After the timeout period

determined by the value in TC4 to TC1, the CP gain bit in the

AB counter latch is automatically reset to 0 and the device

reverts to normal mode instead of fastlock. See Figure 25 for the

timeout periods.

Timer Counter Control

The user has the option of programming two charge pump

currents. The intent is that Current Setting 1 is used when the RF

output is stable and the system is in a static state. Current Setting 2

is meant to be used when the system is dynamic and in a state of

change (that is, when a new output frequency is programmed).

The normal sequence of events is as follows:

The user initially decides what the preferred charge pump

currents are going to be. For example, the choice may be 2.5 mA

as Current Setting 1 and 5 mA as Current Setting 2.

At the same time, it must be decided how long the secondary

current is to stay active before reverting to the primary current.

This is controlled by the timer counter control bits, DB14 to

DB11 (TC4 to TC1), in the function latch. The truth table is

given in Figure 25.

To program a new output frequency, the user simply programs

the AB counter latch with new values for A and B. At the same

time, the CP gain bit can be set to 1, which sets the charge

pump with the value in CPI6 to CPI4 for a period of time

determined by TC4 to TC1. When this time is up, the charge

pump current reverts to the value set by CPI3 to CPI1. At the

same time, the CP gain bit in the AB counter latch is reset to 0

and is ready for the next time that the user wishes to change the

frequency.

Note that there is an enable feature on the timer counter. It is

enabled when Fastlock Mode 2 is chosen by setting the fastlock

mode bit (DB10) in the function latch to 1.

Rev. D | Page 16 of 20

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