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ADE7763ARSRL View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADE7763ARSRL Datasheet PDF : 56 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin No.
15
16
17
18
19
20
Mnemonic
CLKIN
CLKOUT
CS
SCLK
DOUT
DIN
ADE7763
Description
Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.
Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock
source for the ADE7763. The clock frequency for specified operation is 3.579545 MHz. Ceramic load
capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal
manufacturer’s data sheet for load capacitance requirements.
A crystal can be connected across this pin and CLKIN, as described for Pin 15, to provide a clock source for
the ADE7763. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN
or a crystal is being used.
Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7763 to share
the serial bus with several other devices—see the Serial Interface section.
Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this
clock—see the Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source
that has a slow edge transition time, such as an opto-isolator output.
Data Output for the Serial Interface. Data is shifted out at this pin upon the rising edge of SCLK. This logic
output is normally in a high impedance state, unless it is driving data onto the serial data bus—see the
Serial Interface section.
Data Input for the Serial Interface. Data is shifted in at this pin upon the falling edge of SCLK—see the
Serial Interface section.
Rev. A | Page 9 of 56
 

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