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ADE7756AN View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADE7756AN Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin No.
1
2
3
4, 5
6, 7
8
9
10
11
12
13
14
15
16
Mnemonic
RESET
DVDD
AVDD
V1P, V1N
V2N, V2P
AGND
REFIN/OUT
DGND
CF
ZX
SAG
IRQ
CLKIN
CLKOUT
ADE7756
PIN FUNCTION DESCRIPTIONS
Description
Reset Pin for the ADE7756. A logic low on this pin will hold the ADCs and digital circuitry (including
the Serial Interface) in a reset condition.
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7756.
The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7756.
The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to
minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical per-
formance graphs in this data sheet show the power supply rejection performance. This pin should be
decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
Analog Inputs for Channel 1. This channel is intended for use with the current transducer. These
inputs are fully differential voltage inputs with maximum differential input signal levels of ± 1 V, ± 0.5 V
and ± 0.25 V, depending on the full-scale selection. See Analog Inputs section. Channel 1 also has a
PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to
AGND is ± 1 V. Both inputs have internal ESD protection circuitry and in addition an overvoltage of
± 6 V can be sustained on these inputs without risk of permanent damage.
Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These
inputs are fully differential voltage inputs with a maximum differential signal level of ± 1 V. Channel 2
also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with
respect to AGND is ± 1 V. Both inputs have internal ESD protection circuitry, and an overvoltage of
± 6 V can be sustained on these inputs without risk of permanent damage.
This pin provides the ground reference for the analog circuitry in the ADE7756, i.e., ADCs and refer-
ence. This pin should be tied to the analog ground plane or the quietest ground reference in the system.
This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current
and voltage transducers, etc. In order to keep ground noise around the ADE7756 to a minimum, the
quiet ground plane should only be connected to the digital ground plane at one point. It is acceptable
to place the entire device on the analog ground plane—see Applications Information section.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value
of 2.4 V ± 8% and a typical temperature coefficient of 20 ppm/°C. An external reference source may
also be connected at this pin. In either case this pin should be decoupled to AGND with a 1 µF
ceramic capacitor.
This provides the ground reference for the digital circuitry in the ADE7756, i.e., multiplier, filters, and
digital-to-frequency converter. Because the digital return currents in the ADE7756 are small, it is
acceptable to connect this pin to the analog ground plane of the system—see Applications Information
section. However, high bus capacitance on the DOUT pin may result in noisy digital current which
could affect performance.
Calibration Frequency Logic Output. The CF logic output gives Active Power information. This out-
put is intended to be used for operational and calibration purposes. The full-scale output frequency
can be adjusted by writing to the CFDIV Register—see Energy To Frequency Conversion section.
Voltage Waveform (Channel 2) Zero Crossing Output. This output toggles logic high and low at the
zero crossing of the differential signal on Channel 2—see Zero Crossing Detection section.
This open drain logic output goes active low when either no zero crossings are detected or a low volt-
age threshold (Channel 2) is crossed for a specified duration. See Line Voltage Sag Detection section.
Interrupt Request Output. This is an active low open drain logic output. Maskable interrupts include:
Active Energy Register roll-over, Active Energy Register at half level, and arrivals of new waveform
samples—see Interrupts section.
Master clock for ADCs and digital signal processing. An external clock can be provided at this logic
input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to
provide a clock source for the ADE7756. The clock frequency for specified operation is 3.579545 MHz.
Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit.
Refer to crystal manufacturers data sheet for load capacitance requirements.
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the ADE7756. The CLKOUT pin can drive one CMOS load when either an external clock is
supplied at CLKIN or a crystal is being used.
REV. 0
–7–
 

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