ADE7756ARS View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADE7756ARS Datasheet PDF : 32 Pages
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ADE7756
TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
XTAL, TMIN to TMAX = –40؇C to +85؇C, unless otherwise noted.)
Parameter
A, B Versions Unit
Test Conditions/Comments
Write Timing
t1
20
t2
150
t3
150
t4
10
t5
5
t6
6.4
t7
4
t8
100
Read Timing
t9
4
t10
4
t113
30
t124
100
10
t134
100
10
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
µs (min)
µs (min)
ns (min)
µs (min)
µs (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
CS falling edge to first SCLK falling edge.
SCLK logic high pulsewidth.
SCLK logic low pulsewidth.
Valid Data Setup time before falling edge of SCLK.
Data Hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS Hold time after SCLK falling edge.
Minimum time between read command (i.e., a write to Communication
Register) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
Communications Register.
Bus relinquish time after falling edge of SCLK.
Bus relinquish time after rising edge of CS.
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
2See timing diagram below and Serial Interface section of this data sheet.
3Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured
number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics
is the true bus relinquish time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200A
IOL
TO
OUTPUT
PIN
CL
50pF
1.6mA
2.1V
IOH
Figure 1. Load Circuit for Timing Specifications
CS
t1
SCLK
DIN
t8
t2
t3
t4
t5
1 0 0 A4 A3 A2 A1 A0
DB7
t6
t7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
LEAST SIGNIFICANT BYTE
CS
t1
SCLK
t9
t10
t13
REV. 0
DIN
DOUT
0 0 0 A4 A3 A2 A1 A0
t11
DB7
t11
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
Figure 3. Serial Read Timing
–5–
t12
DB7
DB0
LEAST SIGNIFICANT BYTE
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