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ADDAC80-CCD-V View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADDAC80-CCD-V Complete Low Cost 12-Bit D/A Converters ADI
Analog Devices ADI
ADDAC80-CCD-V Datasheet PDF : 16 Pages
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ADDAC80/ADDAC85/ADDAC87
Model
ADDAC80
Min Typ Max
ADDAC85
Min Typ Max
ADDAC87
Min Typ Max
Unit
TEMPERATURE RANGE
Specifications
Operating
Storage
0
+70
–25
+85
–55
+125
°C
–25
+85
–55
+125
–55
+125
°C
–25
+125
–65
+150
–65
+150
°C
NOTES
1Least Significant Bit.
2Adjustable to zero with external trim potentiometer.
3FSR means “Full Scale Range” and is 20 V for the ± 10 V range and 10 V for the ± 5 V range.
4Gain and offset errors adjusted to zero at 25°C.
5CF = 0, see Figure 3a.
6Maximum with no degradation of specification, must be a constant load.
7A minimum of ± 12.3 V is required for a ± 10 V full scale output and ± 11.4 V is required for all other voltage ranges.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
Model
TECHNOLOGY
DIGITAL INPUT
Binary–CBI
BCD–CCD
Logic Levels (TTL Compatible)
VIH (Logic “1”)
VIL (Logic “0”)
IIH (VIH = 5.5 V)
IIL (VIL = 0.8 V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ 25°C
CBI
CCD
TA @ TMIN to TMAX
Differential Linearity Error @ 25°C
CBI
CCD
TA @ TMIN to TMAX
Gain Error2
Offset Error2
Temperature Range for Guaranteed
Monotonicity
DRIFT (TMIN to TMAX)
Total Bipolar Drift, max (includes gain,
offset, and linearity drifts)
Total Error (TMIN to TMAX)4
Unipolar
Bipolar
Gain
Including Internal Reference
Excluding Internal Reference
Unipolar Offset
Bipolar Offset
CONVERSION SPEED
Voltage Model (V)5
Settling Time to ± 0.01% of FSR for
FSR Change (2 kʈ500 pF load)
with 10 kFeedback
with 5 kFeedback
For LSB Change
Slew Rate
Current Model (I)
Settling time to ± 0.01% of FSR for
FSR Change
10 to 100 Load
for 1 k
ADDAC80
Min Typ Max
Hybrid
12
3
2.0
5.5
0
0.8
250
–100
± 1/4 ± 1/2
± 1/8 ± 1/4
± 1/4 ± 1/2
± 1/2
± 1/4
± 0.1
± 0.05
± 3/4
± 1/2
±1
± 0.3
± 0.15
0
+70
± 20
± 0.08 ± 0.15
± 0.06 ± 0.10
± 15 ± 30
±5
±7
±1
±3
±5
± 10
5
3
1.5
10
15
300
1
ADDAC85
Min Typ Max
Hybrid
12
3
2.0
5.5
0
0.8
250
–100
± 1/2
± 1/4
± 1/4 ± 1/2
± 1/2
± 1/2
±1
± 0.1
± 0.05
0
+70
± 20
± 10
±1
± 10
5
3
1.5
20
300
1
ADDAC87
Min Typ Max
Hybrid
12
3
2.0
5.5
0
0.8
250
–100
± 1/2
± 1/4
± 1/2 ± 1/2
± 1/2
± 1/2
±1
± 0.1
± 0.05
–25
+85
± 20
± 10
±1
± 10
5
3
1.5
20
300
1
Unit
Bits
Digits
V
V
µA
µA
LSB1
LSB
LSB
LSB
LSB
LSB
%FSR3
%FSR3
°C
ppm of FSR/°C
% of FSR
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
µs
µs
µs
V/µs
ns
µs
REV. B
–3–
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