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ADC081S101EVAL View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC081S101EVAL 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC081S101EVAL Datasheet PDF : 23 Pages
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ADC121S101/ADC101S101/ADC081S101 Timing Specifications
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, Boldface limits apply for TA = −40˚C to +85˚C:
all other limits TA = 25˚C, unless otherwise noted. (Note 11)
Symbol
Parameter
Conditions
Typical
Limits
Units
tCONVERT
tQUIET
t1
t2
t3
(Note 7)
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS Until SDATA
TRI-STATE® Disabled (Note 8)
16 x tSCLK
50
10
10
20
ns (min)
ns (min)
ns (min)
ns (max)
t4
Data Access Time after SCLK Falling VDD = +2.7 to +3.6
Edge(Note 9)
VDD = +4.75 to +5.25
t5
SCLK Low Pulse Width
t6
SCLK High Pulse Width
t7
SCLK to Data Valid Hold Time
VDD = +2.7 to +3.6
VDD = +4.75 to +5.25
SCLK Falling Edge to SDATA High VDD = +2.7 to +3.6
t8
Impedance (Note 10)
VDD = +4.75 to +5.25
40
20
0.4 x
tSCLK
0.4 x
tSCLK
7
5
25
6
25
5
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
Power-Up Time from Full
tPOWER-UP Power-Down
1
µs
Note 1: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may affect device reliability.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified
Note 3: Specification limit guaranteed by design.
Note 4: See the section titled "Surface Mount" found in a current National Semiconductor Linear Databook for other methods of soldering suface mount devices.
Note 5: Except power supply pins.
Note 6: Independent of supply voltage.
Note 7: Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion
Note 8: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.
Note 9: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.
Note 10: t8 is derived from the time taken by the outputs to change by 0.5V with the loading circuit shown above. The measured number is then adjusted to remove
the effects of charging or discharging the 25pF capacitor. This means t8 is the true bus relinquish time, independent of the bus loading.
Note 11: All input signals are specified as tr = tf = 5 ns (10% to 90% VDD) and timed from 1.6V.
9
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