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ADC08234 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC08234 8-Bit 2ms Serial I/O A/D Converters with MUX, Reference, and Track/Hold National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC08234 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Electrical Characteristics (Continued)
The following specifications apply for VCC e a5 VDC VREF e a2 5 VDC and tr e tf e 20 ns unless otherwise specified
Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
fCLK
Clock Frequency
10
kHz (min)
4
MHz (max)
Clock Duty Cycle
(Note 14)
40
% (min)
60
% (max)
TC
Conversion Time (Not Including
fCLK e 4 MHz
MUX Addressing Time)
8
1 fCLK (max)
2
ms (max)
tCA
tSELECT
tSET-UP
Acquisition Time
CLK High while CS is High
CS Falling Edge or Data Input
Valid to CLK Rising Edge
1
1 fCLK(max)
50
ns
25
ns (min)
tHOLD
Data Input Valid after CLK
Rising Edge
20
ns (min)
tpd1 tpd0
CLK Falling Edge to Output
Data Valid (Note 15)
CL e 100 pF
Data MSB First
Data LSB First
250
200
ns (max)
ns (max)
t1H t0H
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
CL e 10 pF RL e 10 kX
(see TRI-STATE Test Circuits)
50
ns
CL e 100 pF RL e 2 kX
180
ns (max)
CIN
Capacitance of Logic Inputs
5
pF
COUT
Capacitance of Logic Outputs
5
pF
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur
Note 2 Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits For guaranteed
specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance
characteristics may degrade when the device is not operated under the listed test conditions
Note 3 All voltages are measured with respect to AGND e DGND e 0 VDC unless otherwise specified
Note 4 When the input voltage (VIN) at any pin exceeds the power supplies (VIN k (AGND or DGND) or VIN l AVCC ) the current at that pin should be limited to
5 mA The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins
Note 5 The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX iJA and the ambient temperature TA The maximum
allowable power dissipation at any temperature is PD e (TJMAX b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For devices
with suffixes BIN CIN BIJ CIJ BIWM and CIWM TJMAX e 125 C For devices with suffix CMJ TJMAX e 150 C The typical thermal resistances (iJA) of these
parts when board mounted follow ADC08231 with BIN and CIN suffixes 120 C W ADC08234 with BIN and CIN suffixes 95 C W ADC08234 with CIMF suffix
167 C W ADC08238 with BIN and CIN suffixes 80 C W ADC08231 with BIWM and CIWM suffixes 140 C W ADC08234 with BIWM and CIWM suffixes 140 C W
ADC08238 with BIWM and CIWM suffixes 91 C W
Note 6 Human body model 100 pF capacitor discharged through a 1 5 kX resistor
Note 7 See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or Linear Data Book section ‘‘Surface Mount’’ for other methods of
soldering surface mount devices
Note 8 Typicals are at TJ e 25 C and represent the most likely parametric norm
Note 9 Guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 10 Total unadjusted error includes zero full-scale linearity and multiplexer error Total unadjusted error with VREF e a5V only applies to the ADC08234
and ADC08238 See Note 16
Note 11 Cannot be tested for the ADC08231
Note 12 For VIN(b) t VIN(a) the digital code will be 0000 0000 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
for analog input voltages one diode drop below ground or one diode drop greater than VCC supply During testing at low VCC levels (e g 4 5V) high level analog
inputs (e g 5V) can cause an input diode to conduct especially at elevated temperatures This will cause errors for analog inputs near full-scale The specification
allows 50 mV forward bias of either diode this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will
be correct Exceeding this range on an unselected channel will corrupt the reading of a selected channel Achievement of an absolute 0 VDC to 5 VDC input voltage
range will therefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance and loading
Note 13 Channel leakage current is measured after a single-ended channel is selected and the clock is turned off For off channel leakage current the following
two cases are considered one with the selected channel tied high (5 VDC) and the remaining off channels tied low (0 VDC) total current flow through the off
channels is measured two with the selected channel tied low and the off channels tied high total current flow through the off channels is again measured The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured
Note 14 A 40% to 60% duty cycle range insures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock is high or low must be at least 120 ns The maximum time the clock can be high or low is 100 ms
Note 15 Since data MSB first is the output of the comparator used in the successive approximation loop an additional delay is built in (see Block Diagram) to
allow for comparator response time
Note 16 For the ADC08231 VREFIN is internally tied to the on chip 2 5V band-gap reference output therefore the supply current is larger because it includes the
reference current (700 mA typical 2 mA maximum)
Note 17 Load regulation test conditions and specifications for the ADC08231 differ from those of the ADC08234 and ADC08238 because the ADC08231 has the
on-board reference as a permanent load
6
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