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ADC08200CIMT 8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample-and-Hold National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC08200CIMT Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
where tr is the clock rise time and tprop is the propagation rate
of the signal along the trace. Typical tprop is about 150 ps/inch
(59 ps/cm) on FR-4 board material.
If the clock source is used to drive more than just the
ADC08200, the CLOCK pin should be a.c. terminated with a
series RC to ground such that the resistor value is equal to
the characteristic impedance of the clock line and the capac-
itor value is
where tPD is the signal propagation rate down the clock line,
"L" is the line length and ZO is the characteristic impedance
of the clock line. This termination should be located as close
as possible to, but within one centimeter of, the ADC08200
clock pin. Further, this termination should be close to but be-
yond the ADC08200 clock pin as seen from the clock source.
Typical tprop is about 150 ps/inch on FR-4 board material. For
FR-4 board material, the value of C becomes
Where L is the length of the clock line in inches.
This termination should be located as close as possible to,
but within one centimeter of, the ADC08200 clock pin.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. A combined analog and
digital ground plane should be used.
Coupling between the typically noisy digital circuitry and the
sensitive analog circuitry can lead to poor performance that
may seem impossible to isolate and remedy. The solution is
to keep all lines separated from each other by at least six
times the height above the reference plane, and to keep the
analog circuitry well separated from the digital circuitry.
The DR GND connection to the ground plane should not use
the same feedthrough used by other ground connections.
High power digital components should not be located on or
near a straight line between the ADC or any linear component
and the power supply area as the resulting common return
current path could cause fluctuation in the analog input
“ground” return of the ADC.
Generally, analog and digital lines should cross each other at
90° to avoid getting digital noise into the analog path. In high
frequency systems, however, avoid crossing analog and dig-
ital lines altogether. Clock lines should be isolated from ALL
other lines, analog AND digital. Even the generally accepted
90° crossing should be avoided as even a little coupling can
cause problems at high frequencies. Best performance at
high frequencies is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input and ground should be connected to a
very clean point in the ground plane.
FIGURE 5. Layout Example
20017936
Figure 5 gives an example of a suitable layout. All analog cir-
cuitry (input amplifiers, filters, reference components, etc.)
should be placed together away from any digital components.
6.0 DYNAMIC PERFORMANCE
The ADC08200 is a.c. tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must exhibit less than 2 ps (rms)
of jitter. For best a.c. performance, isolating the ADC clock
from any digital circuitry should be done with adequate
buffers, as with a clock tree. See Figure 6.
It is good practice to keep the ADC clock line as short as pos-
sible and to keep it well away from any other signals. Other
signals can introduce jitter into the clock signal. The clock
signal can also introduce noise into the analog path.
20017937
FIGURE 6. Isolating the ADC Clock from Digital Circuitry
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV below the ground pins or 300 mV above
the supply pins. Exceeding these limits on even a transient
basis may cause faulty or erratic operation. It is not uncom-
mon for high speed digital circuits (e.g., 74F and 74AC de-
vices) to exhibit undershoot that goes more than a volt below
ground. A 51resistor in series with the offending digital input
will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC08200. Such practice may lead to conversion inaccura-
cies and even to device damage.
17
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