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ADC08200CIMT 데이터 시트보기 (PDF) - National ->Texas Instruments

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ADC08200CIMT 8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample-and-Hold National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC08200CIMT Datasheet PDF : 20 Pages
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20017933
FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source.
2.0 THE ANALOG INPUT
The analog input of the ADC08200 is a switch followed by an
integrator. The input capacitance changes with the clock lev-
el, appearing as 3 pF when the clock is low, and 4 pF when
the clock is high. The sampling nature of the analog input
causes current spikes at the input that result in voltage spikes
there. Any amplifier used to drive the analog input must be
able to settle within the clock high time. The LMH6702 and
the LMH6628 have been found to be good amplifiers to drive
the ADC08200.
Figure 4 shows an example of an input circuit using the
LMH6702. Any input amplifier should incorporate some gain
as operational amplifiers exhibit better phase margin and
transient response with gains above 2 or 3 than with unity
gain. If an overall gain of less than 3 is required, attenuate the
input and operate the amplifier at a higher gain, as shown in
Figure 4.
The RC at the amplifier output filters the clock rate energy that
comes out of the analog input due to the input sampling circuit.
The optimum time constant for this circuit depends not only
upon the amplifier and ADC, but also on the circuit layout and
board material. A resistor value should be chosen between
18and 47and the capacitor value chose according to the
formula
The value of "C" in the formula above should include the ADC
input capacitance when the clock is high
This will provide optimum SNR performance for Nyquist ap-
plications. Best THD performance is realized when the ca-
pacitor and resistor values are both zero, but this would
compromise SNR and SINAD performance. Generally, the
capacitor should not be added for undersampling applica-
tions.
The circuit of Figure 4 has both gain and offset adjustments.
If you eliminate these adjustments normal circuit tolerances
may result in signal clipping unless care is exercised in the
worst case analysis of component tolerances and the input
signal excursion is appropriately limited to account for the
worst case conditions.
Full scale and offset adjustments may also be made by ad-
justing VRT and VRB, perhaps with the aid of a pair of DACs.
15
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