The ADC08200 uses a new, unique architecture that
achieves over 7 effective bits at input frequencies up to and
beyond 100 MHz.
The analog input signal that is within the voltage range set by
VRT and VRB is digitized to eight bits. Input voltages below
VRB will cause the output word to consist of all zeroes. Input
voltages above VRT will cause the output word to consist of
Incorporating a switched capacitor bandgap, the ADC08200
exhibits a power consumption that is proportional to frequen-
cy, limiting power consumption to what is needed at the clock
rate that is used. This and its excellent performance over a
wide range of clock frequencies makes it an ideal choice as
a single ADC for many 8-bit needs.
Data is acquired at the rising edge of the clock and the digital
equivalent of that data is available at the digital outputs 6 clock
cycles plus tOD later. The ADC08200 will convert as long as
the clock signal is present. The output coding is straight bi-
The device is in the active state when the Power Down pin
(PD) is low. When the PD pin is high, the device is in the power
down mode, where the output pins hold the last conversion
before the PD pin went high and the device consumes just
1.4 mW . Holding the clock input low will further reduce the
power consumption in the power down mode to about 1 mW.
1.0 REFERENCE INPUTS
The reference inputs VRT and VRB are the top and bottom of
the reference ladder, respectively. Input signals between
these two voltages will be digitized to 8 bits. External voltages
applied to the reference input pins should be within the range
specified in the Operating Ratings table. Any device used to
drive the reference pins should be able to source sufficient
current into the VRT pin and sink sufficient current from the
VRB pin to maintain the desired voltages.
FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances, the
reference voltage of this circuit can vary too much for some applications.
The reference bias circuit of Figure 2 is very simple and the
performance is adequate for many applications. However,
circuit tolerances will lead to a wide reference voltage range.
Better reference stability can be achieved by driving the ref-
erence pins with low impedance sources.
The circuit of Figure 3 will allow a more accurate setting of the
reference voltages. The upper amplifier must be able to
source the reference current as determined by the value of
the reference resistor and the value of (VRT − VRB). The lower
amplifier must be able to sink this reference current. Both
amplifiers should be stable with a capacitive load. The
LM8272 was chosen because of its rail-to-rail input and output
capability, its high current output and its ability to drive large
The divider resistors at the inputs to the amplifiers could be
changed to suit the application reference voltage needs, or
the divider can be replaced with potentiometers or DACs for
precise settings. The bottom of the ladder (VRB) may be re-
turned to ground if the minimum input signal excursion is 0V.
VRT should always be more positive than VRB by the minimum
VRT - VRB difference in the Electrical Characteristics table to
minimize noise. While VRT may be as high as the VA supply
voltage and VRB may be as low as ground, the difference be-
tween these two voltages (VRT − VRB) should not exceed 2.3V
to prevent waveform distortion.
The VRM pin is the center of the reference ladder and should
be bypassed to a quiet point in the ground plane with a 0.1 µF
capacitor. DO NOT leave this pin open and DO NOT load this
pin with more than 10µA.