|ADC081500||High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter|
National ->Texas Instruments
|ADC081500 Datasheet PDF : 34 Pages |
2, 5, 8, 13, 16, 17, 20,
25, 28, 33, 128
40, 51 ,62, 73, 88, 99,
1, 6, 9, 12, 21, 24, 27,
The LVDS Data Outputs that are not delayed in the output
demultiplexer. Compared with the Dd outputs, these
outputs represent the later time samples. These outputs
should always be terminated with a 100Ω differential
The LVDS Data Outputs that are delayed by one CLK cycle
in the output demultiplexer. Compared with the D outputs,
these outputs represent the earlier time sample. These
outputs should always be terminated with a 100Ω
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside
the range ±VIN/2 as programmed by the FSR pin in non-
extended control mode or the Input Full-Scale Voltage
Adjust register setting in the extended control mode).
Differential Clock outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input
clock rate in SDR mode and at 1/4 the input clock rate in
the DDR mode. The DCLK outputs are not active during a
calibration cycle. The DCLK outputs are not active during a
calibration cycle, therefore this is not recommended as a
Analog power supply pins. Bypass these pins to ground.
Output Driver power supply pins. Bypass these pins to DR
Ground return for VA.
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