|ADC081500||High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter|
National ->Texas Instruments
|ADC081500 Datasheet PDF : 34 Pages |
Pin Descriptions and Equivalent Circuits
Output Voltage Amplitude and Serial Interface Clock. Tie
this pin high for normal differential DCLK and data
amplitude. Ground this pin for a reduced differential output
amplitude and reduced power consumption. See Section
1.1.6. When the extended control mode is enabled, this pin
functions as the SCLK input which clocks in the serial data.
See Section 1.3
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. (See Section 188.8.131.52).
When this pin is floating or connected to 1/2 the supply
voltage, DDR clocking is enabled. When the extended
control mode is enabled, this pin functions as the (SDATA)
input. See Section 1.2 for details on the extended control
DCLK Reset. A positive pulse on this pin is used to reset
and synchronize the DCLK outputs of multiple converters.
See Section 1.5 for detailed description.
Power Down Pin. A logic high on the PD pin puts the device
into the Power Down Mode.
Calibration Cycle Initiate. A minimum 80 input clock cycles
logic low followed by a minimum of 80 input clock cycles
high on this pin initiates the self calibration sequence. See
Full Scale Range Select and Extended Control Enable. In
non-extended control mode, a logic low on this pin sets the
full-scale differential input range to a reduced VIN input
level . A logic high on this pin sets the full-scale differential
input range to a higher VIN input level. See Converter
Electrical Characteristics. To enable the extended control
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to VA/2. See Section 1.2 for information on the
extended control mode.
Calibration Delay and Serial Interface Chip Select. With a
logic high or low on pin 14, this pin functions as Calibration
Delay and sets the number of input clock cycles after power
up before calibration begins (See Section 1.1.1). With pin
14 floating, this pin acts as the enable pin for the serial
interface input and the CalDly value becomes "0" (short
delay with no provision for a long power-up calibration
|Direct download click here|
|Share Link :|