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ADC081500EVAL View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC081500EVAL High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC081500EVAL Datasheet PDF : 34 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Symbol
Parameter
tRH
Reset Hold Time
tSD
Synchronizing Edge to DCLK
Output Delay
(Note 11)
Conditions
Typical
(Note 8)
250
tOD + tOSK
tRPW
tLHT
tHLT
tOSK
tSU
tH
tAD
tAJ
tOD
tWU
fSCLK
tSSU
tSH
tCAL
tCAL_L
Reset Pulse Width
(Note 11)
Differential Low to High Transition
Time
10% to 90%, CL = 2.5 pF
Differential High to Low Transition
Time
10% to 90%, CL = 2.5 pF
DCLK to Data Output Skew
50% of DCLK transition to 50% of Data
transition, SDR Mode
and DDR Mode, 0° DCLK (Note 11)
Data to DCLK Set-Up Time
DDR Mode, 90° DCLK (Note 11)
DCLK to Data Hold Time
DDR Mode, 90° DCLK (Note 11)
Sampling (Aperture) Delay
Input CLK+ Fall to Acquisition of Data
Aperture Jitter
Input Clock to Data Output Delay 50% of Input Clock transition to 50% of
(in addition to Pipeline Delay) Data transition
Pipeline Delay (Latency)
(Notes 11, 14)
D Outputs
Dd Outputs
Over Range Recovery Time
Differential VIN step from ±1.2V to 0V to
get accurate conversion
PD low to Rated Accuracy
Conversion (Wake-Up Time)
Serial Clock Frequency
(Note 11)
Data to Serial Clock Setup Time (Note 11)
Data to Serial Clock Hold Time (Note 11)
Serial Clock Low Time
Serial Clock High Time
Calibration Cycle Time
250
250
±50
400
560
1.3
0.4
3.1
1
500
100
2.5
1
1.4 x 105
CAL Pin Low Time
See Figure 9 (Note 11)
tCAL_H
tCalDly
CAL Pin High Time
See Figure 9 (Note 11)
Calibration delay determined by
pin 127
CalDly = Low
See Section 1.1.1, Figure 9,
(Note 11)
CalDly = High
See Section 1.1.1, Figure 9,
(Note 11)
Limits
(Note 8)
4
13
14
4
4
80
80
225
231
Units
(Limits)
ps
CLK± Cycles
(min)
ps
ps
ps (max)
ns
ns
ns
ps rms
ns
Input CLK±
Cycles
Input CLK±
Cycle
ns
MHz
ns (min)
ns (min)
ns (min)
ns (min)
CLK± Cycles
CLK± Cycles
(min)
CLK± Cycles
(min)
CLK± Cycles
(min)
CLK± Cycles
(max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kresistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
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