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ADC-208AMC View Datasheet(PDF) - Murata Power Solutions

Part Name
Description
View to exact match
ADC-208AMC
Murata-ps
Murata Power Solutions Murata-ps
ADC-208AMC Datasheet PDF : 4 Pages
1 2 3 4
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Power Supply Voltage (VDD Pin 1, 10, 19)
Digital Inputs
Analog Input
Reference Inputs
Digital Outputs
(short circuit protected to ground)
Lead Temperature (10 sec. max.)
Storage Temperature
LIMITS
–0.5 to +7
–0.5 to +5.5
–0.5 to (+VDD +0.5)
–0.5 to (+VDD +0.5)
–0.5 to +5.5
+300 max.
–65 to +150
UNITS
Volts
Volts
Volts
Volts
Volts
°C
°C
FUNCTIONAL SPECIFICATIONS
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V,
–REFERENCE = ground, unless noted)
ANALOG INPUT
MIN. TYP.
MAX.
Single-Ended, Non-Isolated
Input Range DC - 20MHz
Analog Input Capacitance
(static - Pin 5 to 7)
(dynamic - Pin 5 to 7)
Reference Ladder Resistance
Reference Input (Note 5)
0
+5.0
20
64
500
–0.5
VDD +0.5
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading
Logic Loading "1"
Logic Loading "0"
Clock Low Pulse Width
3.2
0.8
+1
+5
+1
+5
15
25
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading
Logic Loading "1"
Logic Loading "0"
Output Data Valid Delay From
Rising Clock Edge
99% probability
100% probability
+25°C
–55°C to +125°C
Data Output Resolution
Data Coding
2.4
4.5
5.0
0.4
4
4
5
10
15
5
10
25
40
8
Straight binary
PERFORMANCE
Sampling Rate
Full Power Bandwidth
Diff. Linearity @ +25°C
(See tech note 7)
Code Transitions
Center of Codes
Diff. Linearity Over Temp.
Code Transitions
Center of Codes
Int. Linearity @ +25°C
(See tech note 4)(ref. adjusted)
End-point
Best-fit Line
Int. Linearity Over Temp.
(ref. adjusted)
Best-fit Line
15
20
10
±0.5 ±1.0
±0.25 —
±0.5 ±1.0
±0.25 —
±1/2
±1/2
±1/2
±1
UNITS
Volts
pF
pF
Ohms
Volts
Volts
Volts
µA
µA
nSec
Volts
Volts
mA
mA
nSec
nSec
nSec
Bits
MSPS
MHz
LSB
LSB
LSB
LSB
LSB
LSB
LSB
PERFORMANCE
MIN. TYP. MAX. UNITS
Int. Linearity @ +25°C
(ref. unadjusted)
End-point
Best-fit Line
Int. Linearity Over Temp.
(ref. unadjusted)
End-point
Best-fit Line
Zero-Scale Offset
(Code "0" to "1" transition)
Gain Error
Differential Gain
Differential Phase
degrees
Aperture Delay
Aperture Jitter
Harmonic Distortion
(8MHz second order harm.)
Ref. bandwidth
(See tech note 5)
Power Supply Rejection
No Missing Codes
±2
±2.6
LSB
±1.6 ±1.9
LSB
±2.3 ±2.6
LSB
±1.8 ±2.0
LSB
±1
±2
LSB
±1.5
±3
LSB
2
%
1.1
8
ns
50
ps
–40
–46
dB
10
MHz
±0.02 ±0.05 %FSR/%Vs
Over the operating temperature range
POWER REQUIREMENTS
Power Supply Range (+VDD)
Power Supply Current
+25°C
+125°C
–55°C
Power Dissipation
+25°C
+125°C
–55°C
+3.0
+5.0 +5.5
Volts
+45
+65
mA
+40
+60
mA
+50
+70
mA
225
325
mW
200
300
mW
250
350
mW
PHYSiCAL ENVIRONMENTAL
Operating Temp. Range, Case:
MC/LM Versions
MM/LM/QL Versions
Storage Temp. Range
Package Type
DIP
LCC
0
+70
°C
–55
+125
°C
–65
+150
°C
24-pin ceramic DIP
24-pin ceramic LCC
Footnotes:
Maximum input impedance is a function of clock frequency.
At full-power input.
For 10-step, 40 IRE NTSC ramp test.
TECHNICAL NOTES
1. The Reference ladder is floating with respect to VDD and may be referenced anywhere
within the specified limits. AC modulation of the reference voltage may also be utilized; contact
DATEL for further information.
2. Clock Pulse Width – To improve performance when input signals may exceed Nyquist
bandwidths, the clock duty cycle can be adjusted so that the low portion (sample mode) of
the clock pulse is 15nSec wide. Reducing the sampling time period minimizes the amount the
input voltage slews and prevents the comparators from saturating.
3. A full-scale input produces all "1" on the data outputs.
4. DATEL uses the conservative definitions when specifying Intergal Linearity (end-point) and
Differential Linearity (code transition). The specifications using the less conservative definition
have also been provided as a comparative specification for products specified this way.
5. The process that is used to fabricate the ADC-208A eliminates the latchup phenomena
that has plagued CMOS devices in the past. These converters do not require external protec-
tion diodes.
6. For clock rates less than 100kHz, there may be some degradation in offset and differential
nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing
the time spent in the sample mode).
www.murata-ps.com
Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000
MDA_ADC-208A.B01 Page 2 of 4
 

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