7-Bit, 20MHz, CMOS Flash A/D Converters
USING TWO ADC-207’S FOR 8-BIT RESOLUTION
Two ADC-207’s (A and B) are cascadable for applications requir-
ing 8-bit resolution. The device A provides a typical 7-bit output. The
OVERFLOW signal of device A turns off device A and turns on the device B.
The OVERFLOW signal of device A is also used as MSB for 8-bit operation.
The device B provides the other seven bits from the input signal. Figure 4
shows the circuit connections for the application.
4 ANALOG INPUT
BIT 1 (MSB)
Figure 3. Optional Pulse Shaping Circuit
BEAT FREQUENCY AND ENVELOPE TESTS
Figure 5 shows an actual ADC-207 plot of the Beat Frequency Test.
This test uses a 20MHz clock input to the ADC-207 with a 20.002MHz full-
scale sine wave input. Although the converter would not normally be used
in this mode because the input frequency violates Nyquist criteria for full
recovery of signal information, the test is an excellent demonstration of the
ADC-207’s high-frequency performance.
The effect of the 2kHz frequency difference between the input and the
clock is that the output will be a 2kHz sinusoidal digital data array which
"walks" along the actual input at the 2kHz beat note frequency. Any inabil-
ity to follow the 20.002MHz input will be immediately obvious by plotting
the digital data array. Further arithmetic analysis may be done on the data
array to determine spectral purity, harmonic distortion, etc. This test is an
excellent indication of:
1. Full power input bandwidth of all 128 comparators.
(Any gain loss would show as signal distortion.)
2. Phase response linearity vs. instantaneous signal magnitude.
(Phase problems would show as
3. Comparator slew rate limiting.
Figure 6 shows an actual ADC-207 plot of the Envelope Test. This test
is a variation of the previous test but uses a 10.002MHz sinewave input to
give two overlapping cycles when the data is reconstructed by a D/A con-
verter output to an oscilloscope. The scope is triggered by the 20MHz clock
used by the A/D. Any asymmetry between positive and negative portions of
the signal will be very obvious. This test is an excellent indication of slew
rate capability. At the peaks of the envelope, consecutive samples swing
completely through the input voltage range.
Figure 4. Using Two ADC-207’s for 8-Bit Operation
NOTE: The output data bit numbering is offset by a
bit to the device B’s output.
Technical enquiries email: firstname.lastname@example.org, tel: +1 508 339 3000
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