Pin Descriptions and Equivalent Circuits
Output Voltage Amplitude set. Tie this pin high for normal
differential output amplitude. Ground this pin for a reduced
differential output amplitude and reduced power
consumption. See Section 1.5.
Output Edge Select. Sets the edge of the DCLK+ (pin 82) at
which the output data transitions. The output transitions with
the DCLK+ rising edge when this pin is high or on the falling
edge when this pin is low. See Section 5.3.
DC Coupling select. When this pin is high, the VIN+ and VIN-
analog inputs are d.c. coupled and the input common mode
voltage should equal the VCMO (pin 7) output voltage. When
this pin is low, the analog input pins are internally biased and
the input signal should be a.c. coupled to the analog input
pins. See Section 3.0.
Power Down Pin. A logic high on this pin puts the ADC into
the Power Down mode. A logic low on this pin allows normal
Calibration. A minimum 10 clock cycles low followed by a
minimum of 10 clock cycles high on this pin will initiate the
self calibration sequence. See Section 1.1.
Full scale Range Select. With a logic low on this pin, the full-
scale differential input is 600 mVP-P. With a logic high on this
pin, the full-scale differential input is 800 mVP-P. See Section
Calibration Delay. This sets the number of clock cycles after
power up before calibration begins. See Section 1.1.
Clock input pins for the ADC. The differential clock signal
must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+.
Analog Signal Differential Inputs to the ADC.