than is total ground plane volume. Coupling between the typ-
ically noisy digital circuitry and the sensitive analog circuitry
can lead to poor performance that may seem impossible to
isolate and remedy. The solution is to keep the analog cir-
cuitry well separated from the digital circuitry.
High power digital components should not be located on or
near any linear component or power supply trace or plane that
services analog or mixed signal components as the resulting
common return current path could cause fluctuation in the
analog input “ground” return of the ADC, causing excessive
noise in the conversion result.
Generally, we assume that analog and digital lines should
cross each other at 90° to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid
crossing analog and digital lines altogether. Clock lines
should be isolated from ALL other lines, analog AND digital.
The generally accepted 90° crossing should be avoided as
even a little coupling can cause problems at high frequencies.
Best performance at high frequencies is obtained with a
straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. This is
especially important with the low level drive required of the
ADC081000. Any external component (e.g., a filter capacitor)
connected between the converter's input and ground should
be connected to a very clean point in the analog ground plane.
All analog circuitry (input amplifiers, filters, etc.) should be
separated from any digital components.
9.0 DYNAMIC PERFORMANCE
The ADC081000 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications and avoid
jitter-induced noise, the clock source driving the CLK input
must exhibit low rms jitter. The allowable jitter is a function of
the input frequency and the input signal level, as described in
It is good practice to keep the ADC clock line as short as pos-
sible, to keep it well away from any other signals and to treat
it as a transmission line. Other signals can introduce jitter into
the clock signal. The clock signal can also introduce noise into
the analog path if not isolated from that path.
Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than that offered by the package pins.
10.0 COMMON APPLICATION PITFALLS
Allowing loose power supply voltage tolerance. The
ADC081000 is specified for operation between 1.8 Volts to
2.0 Volts. Using a 1.8 Volt power supply then implies the need
for no negative tolerance. The best solution is to use an ad-
justable linear regulator such as the LM317 or LM1086 set for
1.9V as discussed in Section 7.1.
Driving the inputs (analog or digital) beyond the power
supply rails. For device reliability, all inputs should not go
more than 150 mV below the ground pins or 150 mV above
the supply pins. Exceeding these limits on even a transient
basis may not only cause faulty or erratic operation, but may
impair device reliability. It is not uncommon for high speed
digital circuits to exhibit undershoot that goes more than a volt
below ground. Controlling the impedance of high speed lines
and terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the
ADC081000. Such practice may lead to conversion inaccu-
racies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in Sections 1.3 and 3.0, the
Input common mode voltage must remain within 50 mV of the
VCMO output and track that output, which has a variability with
temperature that must also be tracked. Distortion perfor-
mance will be degraded if the input common mode voltage is
more than 50 mV from VCMO.
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC081000 as many high speed amplifiers will have
higher distortion than will the ADC081000, resulting in overall
system performance degradation.
Driving the VBG pin to change the reference voltage. As
mentioned in Section 1.3, the reference voltage is intended to
be fixed to provide one of two different full-scale values (600
mVP-P and 800 mVP-P). Over driving this pin will not change
the full scale value, but can otherwise upset operation.
Driving the clock input with an excessively high level
signal. The ADC clock level should not exceed the level de-
scribed in the Operating Ratings Table or the input offset error
Inadequate clock levels. As described in Section 4.0, insuf-
ficient clock levels can result in poor performance. Excessive
clock levels could result in the introduction of an input offset.
Using an excessively long clock signal trace, or having
other signals coupled to the clock signal trace. This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in
Section 7.2, it is important to provide an adequate heat re-
moval to ensure device reliability. This can either be done with
adequate air flow or the use of a simple heat sink built into the
board. The backside pad should be grounded for best perfor-