datasheetbank_Logo     Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADC081000LEVAL-2004 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC081000LEVAL(2004) High Performance, Low Power 8-Bit, 1 GSPS A/D Converter National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC081000LEVAL Datasheet PDF : 29 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Converter Electrical Characteristics (Continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
800mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, REXT = 3300
± 0.1%, Analog Signal Source Impedance = 100. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C,
unless otherwise stated. (Notes 6, 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
DIGITAL CONTROL PIN CHARACTERISTICS
VIH
Logic High Input Voltage
VIL
Logic Low Input Voltage
II
Input Current
CIN
Logic Input Capacitance (Note 13)
DIGITAL OUTPUT CHARACTERISTICS
(Note 12)
(Note 12)
VIN = 0 or VIN = VA
Each input to ground
1.4
V (min)
0.5
V (max)
±1
µA
1.2
pF
OutV = VA, measured single-ended
300
VOD
LVDS Differential Output Voltage
OutV = GND, measured
225
single-ended
VOD
Change in LVDS Output Swing
±1
DIFF
Between Logic Levels
200
mVP-P (min)
450
mVP-P (max)
140
mVP-P (min)
340
mVP-P (max)
mV
VOS
VOS
Output Offset Voltage
Output Offset Voltage Change
Between Logic Levels
800
mV
±1
mV
Output+ & Output- connected to
IOS
Output Short Circuit Current
0.8V
−4
mA
ZO
Differential Output Impedance
POWER SUPPLY CHARACTERISTICS
100
Ohms
IA
Analog Supply Current
PD = Low
PD = High
646
792
mA (max)
4.5
mA
PD = Low
IDR
Output Driver Supply Current
PD = High
108
160
mA (max)
0.1
mA
PD
Power Consumption
PD = Low
PD = High
1.43
1.8
W (max)
8.7
mW
Change in Offset Error with change
PSRR1 D.C. Power Supply Rejection Ratio
73
dB
in VA from 1.8V to 2.0V
AC ELECTRICAL CHARACTERISTICS
fCLK1
fCLK2
Maximum Conversion Rate
Minimum Conversion Rate
Input Clock Duty Cycle
TA = 85˚C
1.1
TA 75˚C
1.3
TA 70˚C
1.6
200
200 MHz Input clock frequency <
50
1 GHz
1.0
GHz (min)
GHz
GHz
MHz
20
% (min)
80
% (max)
tCL
Input Clock Low Time (Note 12)
tCH
Input Clock High Time (Note 12)
DCLK Duty Cycle (Note 12)
500
200
ps (min)
500
200
ps (min)
45
% (min)
50
55
% (max)
Differential Low to High Transition
tLHT
Time
10% to 90%, CL = 2.5 pF
250
ps
Differential High to Low Transition
tHLT
Time
10% to 90%, CL = 2.5 pF
250
ps
tOSK
DCLK to Data Output Skew
(Note 11)
50% of DCLK transition to 50% of
Data transition
0
±200
ps (max)
Input CLK+ Fall to Acquisition of
tAD
Sampling (Aperture) Delay
Data
930
ps
www.national.com
8
Direct download click here

 

Share Link : 

All Rights Reserved © datasheetbank.com 2014 - 2020 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]