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ADC081000LEVAL-2004 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC081000LEVAL(2004) High Performance, Low Power 8-Bit, 1 GSPS A/D Converter National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC081000LEVAL Datasheet PDF : 29 Pages
First Prev 21 22 23 24 25 26 27 28 29
Functional Description
The ADC081000 is a versatile, high performance, easy to
use A/D Converter with an innovative architecture permitting
very high speed operation. The controls available ease the
application of the device to circuit solutions. The ADC081000
uses a calibrated folding and interpolating architecture that
achieves over 7.5 effective bits. The use of folding amplifiers
greatly reduces the number of comparators and power con-
sumption, while Interpolation reduces the number of front-
end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter. Optimum per-
formance requires adherence to the provisions discussed
here and in the Applications Information Section.
1.0 OVERVIEW
The analog input signal that is within the converter’s input
voltage range is digitized to eight bits at speeds of 200
MSPS to 1.6 GSPS, typical. Differential input voltages below
negative full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. The OR (Out
of Range) output is activated whenever the correct output
code would be outside of the 00h to FFh range.
The converter has a 1:2 demultiplexer that feeds two LVDS
output buses. The data on these buses provide an output
word rate on each bus at half the ADC sampling rate and
must be interleaved by the user to provide output words at
the full conversion rate.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erro-
neous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
The voltage reference for the ADC081000 is derived from a
1.254V bandgap reference which is made available to the
user at the VBG pin. This output is capable of sourcing or
sinking ±100 µA.
The internal bandgap derived reference voltage has a nomi-
nal value of 600 mV or 800 mV, as determined by the FSR
pin and described in Section 1.3. There is no provision for
the use of an external reference voltage.
The fully differential comparator design and the innovative
design of the sample-and-hold amplifier, together with self
calibration, enables flat SINAD/ENOB response beyond 1.0
GHz. The ADC081000 output data signaling is LVDS and the
output format is offset binary.
1.1 Self-Calibration
A self-calibration is performed upon power-up and can also
be invoked by the user upon command. Calibration trims the
100analog input differential termination resistor and mini-
mizes full-scale error, offset error, DNL and INL, resulting in
maximizing SNR, THD, SINAD (SNDR), SFDR and ENOB.
Internal bias currents are also set with the calibration pro-
cess. All of this is true whether the calibration is performed
upon power up or is performed upon command.
Running the self calibration is important for this chip’s func-
tionality and is required in order to obtain adequate perfor-
mance. In addition to the requirement to be run at power-up,
self calibration must be re-run whenever the sense of the
FSR pin is changed.
For best performance, we recommend that self calibration
be run 20 seconds or more after application of power and
whenever the operating ambient temperature changes more
than 30˚C since calibration was last performed. See Section
5.1.2 for more information.
During the calibration process, the input termination resistor
is trimmed to a value that is equal to REXT / 33. This external
resistor must be placed between pin 32 and ground and
must be 3300 ±0.1%. With this value, the input termina-
tion resistor is trimmed to be 100 . Because REXT is also
used to set the proper bias current for the Track and Hold
amplifier, for the preamplifiers and for the comparators, other
values of REXT should not be used.
In normal operation, calibration is performed just after appli-
cation of power and whenever a valid calibration command
is given, which is holding the CAL pin low for at least 10 clock
cycles, then holding it high for at least another 10 clock
cycles. There is no need to bring the CAL pin low after the 10
clock cycles of CAL high to begin the calibration routine.
Holding the CAL pin high upon power up, however, will
prevent the calibration process from running until the CAL
pin experiences the above-mentioned 10 clock cycles low
followed by 10 cycles high.
The CalDly pin is used to select one of two delay times after
the application of power to the start of calibration. This
calibration delay is 224 clock cycles (about 16.8 ms at 1
GSPS) with CalDly low, or 230 clock cycles (about 1.07
seconds at 1 GSPS) with CalDly high. These delay values
allow the power supply to come up and stabilize before
calibration takes place. If the PD pin is high upon power-up,
the calibration delay counter will be disabled until the PD pin
is brought low. Therefore, holding the PD pin high during
power up will further delay the start of the power-up calibra-
tion cycle. The best setting of the CalDly pin depends upon
the power-on settling time of the power supply.
The CalRun output is high whenever the calibration proce-
dure is running. This is true whether the calibration is done at
power-up or on-command.
Calibration can not be initiated or run while the device is in
the power-down mode. See Section 1.7 for information on
the interaction between Power Down and Calibration.
1.2 Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the
digital equivalent of that data is available at the digital out-
puts 7 clock cycles later for the "D" output bus and 8 clock
cycles later for the "Dd" output bus. There is an additional
internal delay called tOD before the data is available at the
outputs. See the Timing Diagram. The ADC081000 will con-
vert as long as the clock signal is present and the PD pin is
low.
1.3 The Analog Inputs
The ADC081000 must be driven with a differential input
signal. It is important that the inputs either be a.c. coupled to
the inputs with the DC_Coup pin grounded or d.c. coupled
with the DC_Coup pin high and have an input common mode
voltage that is equal to and tracks the VCMO output.
Two full-scale range settings are provided with the FSR pin.
A high on that pin causes an input differential full-scale range
setting of 800 mVP-P, while grounding that pin causes an
input differential full-scale range setting of 600 mVP-P.
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