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ADC0805 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC0805 8-Bit µP Compatible A/D Converters National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC0805 Datasheet PDF : 41 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC) (Note 3)
Voltage
Logic Control Inputs
At Other Input and Outputs
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
6.5V
−0.3V to +18V
−0.3V to (VCC+0.3V)
260˚C
300˚C
215˚C
Infrared (15 seconds)
Storage Temperature Range
Package Dissipation at TA=25˚C
ESD Susceptibility (Note 10)
220˚C
−65˚C to +150˚C
875 mW
800V
Operating Ratings (Notes 1, 2)
Temperature Range
ADC0804LCJ
ADC0801/02/03/05LCN
ADC0804LCN
ADC0802/04LCWM
Range of VCC
TMINTATMAX
−40˚CTA+85˚C
−40˚CTA+85˚C
0˚CTA+70˚C
0˚CTA+70˚C
4.5 VDC to 6.3 VDC
Electrical Characteristics
The following specifications apply for VCC=5 VDC, TMINTATMAX and fCLK=640 kHz unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
ADC0801: Total Adjusted Error (Note 8)
With Full-Scale Adj.
±14
(See Section 2.5.2)
ADC0802: Total Unadjusted Error (Note 8)
VREF/2=2.500 VDC
±12
ADC0803: Total Adjusted Error (Note 8)
With Full-Scale Adj.
±12
(See Section 2.5.2)
ADC0804: Total Unadjusted Error (Note 8)
ADC0805: Total Unadjusted Error (Note 8)
VREF/2 Input Resistance (Pin 9)
VREF/2=2.500 VDC
VREF/2-No Connection
ADC0801/02/03/05
ADC0804 (Note 9)
±1
±1
2.5
8.0
0.75
1.1
Analog Input Voltage Range
DC Common-Mode Error
(Note 4) V(+) or V(−)
Over Analog Input Voltage
Gnd–0.05
±1/16
VCC+0.05
±18
Range
Power Supply Sensitivity
VCC=5 VDC ±10% Over
Allowed VIN(+) and VIN(−)
Voltage Range (Note 4)
±1/16
±18
Units
LSB
LSB
LSB
LSB
LSB
k
k
VDC
LSB
LSB
AC Electrical Characteristics
The following specifications apply for VCC=5 VDC and TMINTATMAX unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max
TC
Conversion Time
TC
Conversion Time
fCLK
Clock Frequency
Clock Duty Cycle
fCLK=640 kHz (Note 6)
(Notes 5, 6)
VCC=5V, (Note 5)
103
114
66
73
100 640 1460
40
60
CR
Conversion Rate in Free-Running
INTR tied to WR with
8770
9708
tW(WR)L
tACC
Mode
Width of WR Input (Start Pulse Width)
Access Time (Delay from Falling
Edge of RD to Output Data Valid)
CS =0 VDC, fCLK=640 kHz
CS =0 VDC (Note 7)
CL=100 pF
100
135 200
t1H, t0H
TRI-STATE Control (Delay
from Rising Edge of RD to
CL=10 pF, RL=10k
(See TRI-STATE Test
125 200
Hi-Z State)
Circuits)
tWI, tRI
Delay from Falling Edge
of WR or RD to Reset of INTR
300 450
CIN
Input Capacitance of Logic
Control Inputs
5
7.5
Units
µs
1/fCLK
kHz
%
conv/s
ns
ns
ns
ns
pF
3
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