Functional Description (Continued)
3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been as-
signed and a conversion is about to begin. An interval of
1⁄2 clock period (where nothing happens) is automatically
inserted to allow the selected MUX channel to settle.
The SARS line goes high at this time to signal that a con-
version is now in progress and the DI line is disabled (it
no longer accepts data).
4. The data out (DO) line now comes out of TRI-STATE
and provides a leading zero for this one clock period of
MUX settling time.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gener-
ated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conver-
sion being shifted out (with the MSB first) and can be
read by the processor immediately.
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this 1⁄2 clock cycle later.
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers the data can be provided in an LSB first format
[this makes use of the shift enable (SE) control line]. On
the ADC08038 the SE line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE is forced low the data is clocked out LSB first. On de-
vices which do not include the SE control line, the data,
LSB first, is automatically shifted out the DO line after
the MSB first data stream. The DO line then goes low
and stays low until CS is returned high. The ADC08031
is an exception in that its data is only output in MSB first
8. All internal registers are cleared when the CS line is high
and the tSELECT requirement is met. See Data Input Tim-
ing under Timing Diagrams. If another conversion is de-
sired CS must make a high to low transition followed by
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only “looked-at”
during the MUX addressing interval while the DO line is
still in a high impedance state.
FIGURE 1. Analog Input Multiplexer Options for the ADC08038