AD9879 View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
AD9879 Datasheet PDF : 32 Pages
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AD9879
Parameter
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation (AOUT = 5 MHz)
Isolation Between Tx and IQ ADCs
Isolation Between Tx and 10-Bit ADC
Isolation Between Tx and 12-Bit ADC
ADC-to-ADC (AIN = –0.5 dBFS, f = 5 MHz)
Isolation Between IF10 and IF12 ADCs
Isolation Between Q and I Inputs
TIMING CHARACTERISTICS (10 pF Load)
Minimum RESET Pulse Width Low (tRL)
Digital Output Rise/Fall Time
Tx/Rx Interface
MCLK Frequency (fMCLK)
TxSYNC/TxIQ Setup Time (tSU)
TxSYNC/TxIQ Hold Time (tHD)
MCLK Rising Edge to
RxSYNC/RxIQ/IF Valid Delay (tMD)
REFCLK Rising or Falling Edge to
RxSYNC/RxIQ/IF Valid Delay (tOD)
REFCLK Edge to MCLK Falling Edge (tEE)
Serial Control Bus
Maximum SCLK Frequency (fSCLK)
Minimum Clock Pulse Width High (tPWH)
Minimum Clock Pulse Width Low (tPWL)
Maximum Clock Rise/Fall Time
Minimum Data/Chip-Select Setup Time (tDS)
Minimum Data Hold Time (tDH)
Maximum Data Valid Time (tDV)
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY
Supply Current, IS (Full Operation)
Analog Supply Current, IAS
Digital Supply Current, IDS
Supply Current, IS
Standby (PWRDN Pin Active)
Full Power-Down (Register 0x02 = 0xF9)
Power-Down Tx Path (Register 0x02 = 0x60)
Power-Down Rx Path (Register 0x02 = 0x19)
Temp Test Level Min
Full II
46.2
Full II
Full II
44.9
25°C III
25°C III
25°C III
25°C III
25°C III
N/A N/A
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
25°C II
25°C II
25°C II
25°C II
25°C II
25°C II
25°C II
25°C II
25°C III
25°C III
25°C II
25°C III
25°C III
25°C III
5
2.8
3
3
0
TOSC/4 – 2.0
−1.0
30
30
25
0
VDRVDD – 0.7
VDRVDD – 0.6
1 IQ ADC in default mode. ADC Clock Select Register 8, Bit 3 set to 0.
Typ
57.2
−50.1
53.4
>60
>80
>80
>85
>50
3
163
95
68
119
16
113
110
Max
Unit
Bits
−44.5
dB
dB
4
66
1.0
TOSC/4 + 3.0
+1.0
15
1
30
0.4
12
12
0.4
184
126
dB
dB
dB
dB
dB
tMCLK cycles
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ms
ns
ns
ns
V
V
µA
µA
pF
V
V
mA
mA
mA
mA
mA
mA
mA
Rev. A | Page 6 of 32
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